Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7cc33411 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Remove 4xx support 



Remove 4xx support from the msm-4.19 kernel. We are unlikely to see
any more targets from this family again and removing it also obsoletes
a number of larger workarounds and hacks that were made to accommodate
quirks in the 4xx family which will be removed in the following
patches.

Change-Id: Ic0dedbad890e9f9b20a9d3e1ea7a31d628323870
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent fa567ab2

drivers/gpu/msm/Makefile

+0 −3
Original line number Diff line number Diff line
@@ -32,14 +32,11 @@ msm_adreno-y += \ 
	adreno_coresight.o \

	adreno_trace.o \

	adreno_a3xx.o \

	adreno_a4xx.o \

	adreno_a5xx.o \

	adreno_a6xx.o \

	adreno_a3xx_snapshot.o \

	adreno_a4xx_snapshot.o \

	adreno_a5xx_snapshot.o \

	adreno_a6xx_snapshot.o \

	adreno_a4xx_preempt.o \

	adreno_a5xx_preempt.o \

	adreno_a6xx_preempt.o \

	adreno_a6xx_gmu.o \

drivers/gpu/msm/a4xx_reg.h

deleted100644 → 0
+0 −839

File deleted.

Preview size limit exceeded, changes collapsed.

drivers/gpu/msm/adreno-gpulist.h

+4 −57
Original line number Diff line number Diff line
@@ -51,12 +51,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 0,

		.minor = 5,

		.patchid = ANY_ID,

		.features = ADRENO_SOFT_FAULT_DETECT,

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

		.gmem_size = SZ_256K,

		.busy_mask = 0x7FFFFFFE,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A420,
@@ -64,20 +59,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 2,

		.minor = 0,

		.patchid = ANY_ID,

		.features = ADRENO_USES_OCMEM | ADRENO_WARM_START |

			ADRENO_USE_BOOTSTRAP | ADRENO_SOFT_FAULT_DETECT,

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

		.gmem_size = (SZ_1M + SZ_512K),

		.pm4_jt_idx = 0x901,

		.pm4_jt_addr = 0x300,

		.pfp_jt_idx = 0x401,

		.pfp_jt_addr = 0x400,

		.pm4_bstrp_size = 0x06,

		.pfp_bstrp_size = 0x28,

		.pfp_bstrp_ver = 0x4ff083,

		.busy_mask = 0x7FFFFFFE,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A430,
@@ -85,25 +67,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 3,

		.minor = 0,

		.patchid = ANY_ID,

		.features = ADRENO_USES_OCMEM  | ADRENO_WARM_START |

			ADRENO_USE_BOOTSTRAP | ADRENO_SPTP_PC | ADRENO_PPD |

			ADRENO_CONTENT_PROTECTION | ADRENO_PREEMPTION |

			ADRENO_SOFT_FAULT_DETECT,

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

		.gmem_size = (SZ_1M + SZ_512K),

		.pm4_jt_idx = 0x901,

		.pm4_jt_addr = 0x300,

		.pfp_jt_idx = 0x401,

		.pfp_jt_addr = 0x400,

		.pm4_bstrp_size = 0x06,

		.pfp_bstrp_size = 0x28,

		.pfp_bstrp_ver = 0x4ff083,

		.shader_offset = 0x20000,

		.shader_size = 0x10000,

		.num_protected_regs = 0x18,

		.busy_mask = 0x7FFFFFFE,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A418,
@@ -111,24 +75,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 1,

		.minor = 8,

		.patchid = ANY_ID,

		.features = ADRENO_USES_OCMEM  | ADRENO_WARM_START |

			ADRENO_USE_BOOTSTRAP | ADRENO_SPTP_PC |

			ADRENO_SOFT_FAULT_DETECT,

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

		.gmem_size = (SZ_512K),

		.pm4_jt_idx = 0x901,

		.pm4_jt_addr = 0x300,

		.pfp_jt_idx = 0x401,

		.pfp_jt_addr = 0x400,

		.pm4_bstrp_size = 0x06,

		.pfp_bstrp_size = 0x28,

		.pfp_bstrp_ver = 0x4ff083,

		.shader_offset = 0x20000, /* SP and TP addresses */

		.shader_size = 0x10000,

		.num_protected_regs = 0x18,

		.busy_mask = 0x7FFFFFFE,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A530,

drivers/gpu/msm/adreno.c

+0 −3
Original line number Diff line number Diff line
@@ -1731,9 +1731,6 @@ static void _set_secvid(struct kgsl_device *device) 


	/* Program GPU contect protection init values */

	if (device->mmu.secured && !set) {

		if (adreno_is_a4xx(adreno_dev))

			adreno_writereg(adreno_dev,

				ADRENO_REG_RBBM_SECVID_TRUST_CONFIG, 0x2);

		adreno_writereg(adreno_dev,

				ADRENO_REG_RBBM_SECVID_TSB_CONTROL, 0x0);

drivers/gpu/msm/adreno.h

+1 −55
Original line number Diff line number Diff line
@@ -17,8 +17,6 @@ 
#include <linux/delay.h>

#include "kgsl_gmu_core.h"



#include "a4xx_reg.h"



#ifdef CONFIG_QCOM_OCMEM

#include <soc/qcom/ocmem.h>

#endif
@@ -85,8 +83,6 @@ 
#define ADRENO_USES_OCMEM     BIT(0)

/* The core supports an accelerated warm start */

#define ADRENO_WARM_START     BIT(1)

/* The core supports the microcode bootstrap functionality */

#define ADRENO_USE_BOOTSTRAP  BIT(2)

/* The core supports SP/TP hw controlled power collapse */

#define ADRENO_SPTP_PC BIT(3)

/* The core supports Peak Power Detection(PPD)*/
@@ -289,8 +285,6 @@ enum adreno_preempt_states { 
 * preemption counters on switch

 * @timer: A timer to make sure preemption doesn't stall

 * @work: A work struct for the preemption worker (for 5XX)

 * @token_submit: Indicates if a preempt token has been submitted in

 * current ringbuffer (for 4XX)

 * preempt_level: The level of preemption (for 6XX)

 * skipsaverestore: To skip saverestore during L1 preemption (for 6XX)

 * usesgmem: enable GMEM save/restore across preemption (for 6XX)
@@ -301,7 +295,6 @@ struct adreno_preemption { 
	struct kgsl_memdesc counters;

	struct timer_list timer;

	struct work_struct work;

	bool token_submit;

	unsigned int preempt_level;

	bool skipsaverestore;

	bool usesgmem;
@@ -1107,7 +1100,6 @@ extern unsigned int adreno_ft_regs_num; 
extern unsigned int *adreno_ft_regs_val;



extern struct adreno_gpudev adreno_a3xx_gpudev;

extern struct adreno_gpudev adreno_a4xx_gpudev;

extern struct adreno_gpudev adreno_a5xx_gpudev;

extern struct adreno_gpudev adreno_a6xx_gpudev;
@@ -1234,30 +1226,6 @@ static inline int adreno_is_a330v21(struct adreno_device *adreno_dev) 
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) > 0xF));

}



static inline int adreno_is_a4xx(struct adreno_device *adreno_dev)

{

	return ADRENO_GPUREV(adreno_dev) >= 400 &&

		ADRENO_GPUREV(adreno_dev) < 500;

}



ADRENO_TARGET(a405, ADRENO_REV_A405);



static inline int adreno_is_a405v2(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A405) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0x10);

}



ADRENO_TARGET(a418, ADRENO_REV_A418)

ADRENO_TARGET(a420, ADRENO_REV_A420)

ADRENO_TARGET(a430, ADRENO_REV_A430)



static inline int adreno_is_a430v2(struct adreno_device *adreno_dev)

{

	return ((ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A430) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1));

}



static inline int adreno_is_a5xx(struct adreno_device *adreno_dev)

{

	return ADRENO_GPUREV(adreno_dev) >= 500 &&
@@ -1349,7 +1317,7 @@ static inline bool adreno_checkreg_off(struct adreno_device *adreno_dev, 
	 * programming needs to be skipped for certain GPU cores.

	 * Example: Certain registers on a5xx like IB1_BASE are 64 bit.

	 * Common programming programs 64bit register but upper 32 bits

	 * are skipped in a4xx and a3xx using ADRENO_REG_SKIP.

	 * are skipped in a3xx using ADRENO_REG_SKIP.

	 */

	if (gpudev->reg_offsets->offsets[offset_name] == ADRENO_REG_SKIP)

		return false;
@@ -1616,17 +1584,6 @@ static inline void adreno_set_protected_registers( 
					*index, max_slots))

		return;



	/*

	 * On A4XX targets with more than 16 protected mode registers

	 * the upper registers are not contiguous with the lower 16

	 * registers so we have to adjust the base and offset accordingly

	 */



	if (adreno_is_a4xx(adreno_dev) && *index >= 0x10) {

		base = A4XX_CP_PROTECT_REG_10;

		offset = *index - 0x10;

	}



	val = 0x60000000 | ((mask_len & 0x1F) << 24) | ((reg << 2) & 0xFFFFF);



	kgsl_regwrite(KGSL_DEVICE(adreno_dev), base + offset, val);
@@ -1678,17 +1635,6 @@ static inline int adreno_compare_pfp_version(struct adreno_device *adreno_dev, 
	return (adreno_dev->fw[ADRENO_FW_PFP].version > version) ? 1 : -1;

}



/*

 * adreno_bootstrap_ucode() - Checks if Ucode bootstrapping is supported

 * @adreno_dev:		Pointer to the the adreno device

 */

static inline int adreno_bootstrap_ucode(struct adreno_device *adreno_dev)

{

	return (ADRENO_FEATURE(adreno_dev, ADRENO_USE_BOOTSTRAP) &&

		adreno_compare_pfp_version(adreno_dev,

			adreno_dev->gpucore->pfp_bstrp_ver) >= 0) ? 1 : 0;

}



/**

 * adreno_in_preempt_state() - Check if preemption state is equal to given state

 * @adreno_dev: Device whose preemption state is checked