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Commit fa567ab2 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Remove obsolete pre-production targets 



We do not need to carry support for old pre-production GPU spins from
older kernels as we expect only the production version of that GPU
to be in active use from this point on.

Change-Id: Ic0dedbad1de068efedb5d76d271ea489d81b95f3
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent a0fb6443

drivers/gpu/msm/adreno-gpulist.h

+4 −61
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.

 */
@@ -136,12 +136,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 3,

		.minor = 0,

		.patchid = 0,

		.pm4fw_name = "a530v1_pm4.fw",

		.pfpfw_name = "a530v1_pfp.fw",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A530,
@@ -242,21 +237,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 4,

		.minor = 0,

		.patchid = 0,

		.features = ADRENO_PREEMPTION | ADRENO_64BIT |

			ADRENO_CONTENT_PROTECTION |

			ADRENO_GPMU | ADRENO_SPTP_PC,

		.pm4fw_name = "a530_pm4.fw",

		.pfpfw_name = "a530_pfp.fw",

		.zap_name = "a540_zap",

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a540_gpmu.fw2",

		.gpmu_major = 3,

		.gpmu_minor = 0,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A540,
@@ -318,21 +299,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.major = 3,

		.minor = 0,

		.patchid = 0,

		.features = ADRENO_64BIT | ADRENO_RPMH |

			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_LM,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a630_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_size = SZ_1M,

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a630_gmu.bin",

		.gpmu_major = 0x1,

		.gpmu_minor = 0x003,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.prim_fifo_threshold = 0x0018000,

		.pdc_address_offset = 0x00030080,

		.features = ADRENO_DEPRECATED,

	},

	{

		.gpurev = ADRENO_REV_A630,
@@ -399,30 +366,6 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.prim_fifo_threshold = 0x0018000,

		.pdc_address_offset = 0x00030090,

	},

	{

		.gpurev = ADRENO_REV_A640,

		.core = 6,

		.major = 4,

		.minor = 0,

		.patchid = 0,

		.features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU |

			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |

			ADRENO_IFPC,

		.sqefw_name = "a630_sqe.fw",

		.zap_name = "a640_zap",

		.gpudev = &adreno_a6xx_gpudev,

		.gmem_size = SZ_1M, //Verified 1MB

		.num_protected_regs = 0x20,

		.busy_mask = 0xFFFFFFFE,

		.gpmufw_name = "a640_gmu.bin",

		.gpmu_major = 0x2,

		.gpmu_minor = 0x000,

		.gpmu_tsens = 0x000C000D,

		.max_power = 5448,

		.va_padding = SZ_64K,

		.prim_fifo_threshold = 0x00200000,

		.pdc_address_offset = 0x00030090,

	},

	{

		.gpurev = ADRENO_REV_A640,

		.core = 6,

drivers/gpu/msm/adreno.c

+6 −45
Original line number Diff line number Diff line
@@ -499,17 +499,6 @@ static int _soft_reset(struct adreno_device *adreno_dev) 
	struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	unsigned int reg;



	/*

	 * On a530 v1 RBBM cannot be reset in soft reset.

	 * Reset all blocks except RBBM for a530v1.

	 */

	if (adreno_is_a530v1(adreno_dev)) {

		adreno_writereg(adreno_dev, ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD,

						 0xFFDFFC0);

		adreno_writereg(adreno_dev, ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD2,

						0x1FFFFFFF);

	} else {



	adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 1);

	/*

	 * Do a dummy read to get a brief read cycle delay for the
@@ -517,7 +506,6 @@ static int _soft_reset(struct adreno_device *adreno_dev) 
	 */

	adreno_readreg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, &reg);

	adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 0);

	}



	/* The SP/TP regulator gets turned off after a soft reset */
@@ -1368,14 +1356,6 @@ static int adreno_probe(struct platform_device *pdev) 
	if (adreno_support_64bit(adreno_dev))

		device->mmu.features |= KGSL_MMU_64BIT;



	/* Default to 4K alignment (in other words, no additional padding) */

	device->mmu.va_padding = PAGE_SIZE;



	if (adreno_dev->gpucore->va_padding) {

		device->mmu.features |= KGSL_MMU_PAD_VA;

		device->mmu.va_padding = adreno_dev->gpucore->va_padding;

	}



	status = kgsl_device_platform_probe(device);

	if (status) {

		device->pdev = NULL;
@@ -1657,9 +1637,7 @@ static int adreno_init(struct kgsl_device *device) 
			return ret;

	}



	ret = adreno_iommu_init(adreno_dev);

	if (ret)

		return ret;

	 adreno_iommu_init(adreno_dev);



	adreno_perfcounter_init(adreno_dev);

	adreno_fault_detect_init(adreno_dev);
@@ -1882,23 +1860,6 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
		_soft_reset(adreno_dev);





	if (adreno_is_a640v1(adreno_dev)) {

		unsigned long start = jiffies;



		if (scm_is_call_available(SCM_SVC_MP, CP_SMMU_APERTURE_ID)) {

			ret = kgsl_program_smmu_aperture();

			/* Log it if it takes more than 2 seconds */

			if (((jiffies - start) / HZ) > 2)

				dev_err(device->dev, "scm call took too long to finish on a640v1: %lu seconds\n",

					((jiffies - start) / HZ));

			if (ret) {

				dev_err(device->dev, "SMMU aperture programming call failed with error %d\n",

					ret);

				goto error_pwr_off;

			}

		}

	}



	adreno_ringbuffer_set_global(adreno_dev, 0);



	status = kgsl_mmu_start(device);

drivers/gpu/msm/adreno.h

+0 −38
Original line number Diff line number Diff line
@@ -391,7 +391,6 @@ struct adreno_device_private { 
 * @regfw_name: Filename for the register sequence firmware

 * @gpmu_tsens: ID for the temporature sensor used by the GPMU

 * @max_power: Max possible power draw of a core, units elephant tail hairs

 * @va_padding: Size to pad allocations to, zero if not required

 */

struct adreno_gpu_core {

	enum adreno_gpurev gpurev;
@@ -422,7 +421,6 @@ struct adreno_gpu_core { 
	const char *regfw_name;

	unsigned int gpmu_tsens;

	unsigned int max_power;

	uint64_t va_padding;

	unsigned int prim_fifo_threshold;

	unsigned int pdc_address_offset;

};
@@ -1274,12 +1272,6 @@ ADRENO_TARGET(a512, ADRENO_REV_A512) 
ADRENO_TARGET(a530, ADRENO_REV_A530)

ADRENO_TARGET(a540, ADRENO_REV_A540)



static inline int adreno_is_a530v1(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A530) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0);

}



static inline int adreno_is_a530v2(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A530) &&
@@ -1298,18 +1290,6 @@ static inline int adreno_is_a505_or_a506(struct adreno_device *adreno_dev) 
			ADRENO_GPUREV(adreno_dev) <= 506;

}



static inline int adreno_is_a540v1(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A540) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0);

}



static inline int adreno_is_a540v2(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A540) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1);

}



static inline int adreno_is_a6xx(struct adreno_device *adreno_dev)

{

	return ADRENO_GPUREV(adreno_dev) >= 600 &&
@@ -1343,24 +1323,6 @@ static inline int adreno_is_a640_family(struct adreno_device *adreno_dev) 
			rev == ADRENO_REV_A680);

}



static inline int adreno_is_a630v1(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A630) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0);

}



static inline int adreno_is_a630v2(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A630) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1);

}



static inline int adreno_is_a640v1(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A640) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0);

}



static inline int adreno_is_a640v2(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A640) &&

drivers/gpu/msm/adreno_a5xx.c

+13 −48
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.

 */



#include <linux/firmware.h>
@@ -1873,11 +1873,9 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
	}



	/*

	 * Turn on hang detection for a530 v2 and beyond. This spews a

	 * lot of useful information into the RBBM registers on a hang.

	 * Turn on hang detection. This spews a lot of useful information

	 * into the RBBM registers on a hang.

	 */

	if (!adreno_is_a530v1(adreno_dev)) {



	set_bit(ADRENO_DEVICE_HANG_INTR, &adreno_dev->priv);

	gpudev->irq->mask |= (1 << A5XX_INT_MISC_HANG_DETECT);

	/*
@@ -1886,8 +1884,6 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
	 */

	kgsl_regwrite(device, A5XX_RBBM_INTERFACE_HANG_INT_CNTL,

				  (1 << 30) | 0x3FFFF);

	}





	/* Turn on performance counters */

	kgsl_regwrite(device, A5XX_RBBM_PERFCTR_CNTL, 0x01);
@@ -1956,19 +1952,6 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
		kgsl_regwrite(device, A5XX_PC_DBG_ECO_CNTL,

						(0x400 << 11 | 0x300 << 22));



	/*

	 * A5x USP LDST non valid pixel wrongly update read combine offset

	 * In A5xx we added optimization for read combine. There could be cases

	 * on a530 v1 there is no valid pixel but the active masks is not

	 * cleared and the offset can be wrongly updated if the invalid address

	 * can be combined. The wrongly latched value will make the returning

	 * data got shifted at wrong offset. workaround this issue by disabling

	 * LD combine, bit[25] of SP_DBG_ECO_CNTL (sp chicken bit[17]) need to

	 * be set to 1, default is 0(enable)

	 */

	if (adreno_is_a530v1(adreno_dev))

		kgsl_regrmw(device, A5XX_SP_DBG_ECO_CNTL, 0, (1 << 25));



	if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_TWO_PASS_USE_WFI)) {

		/*

		 * Set TWOPASSUSEWFI in A5XX_PC_DBG_ECO_CNTL for
@@ -2253,14 +2236,6 @@ static int _me_init_ucode_workarounds(struct adreno_device *adreno_dev) 
		 * WFI after every 2D Mode 3 draw.

		 */

		return 0x0000000B;

	case ADRENO_REV_A540:

		/*

		 * WFI after every direct-render 3D mode draw and

		 * WFI after every 2D Mode 3 draw. This is needed

		 * only on a540v1.

		 */

		if (adreno_is_a540v1(adreno_dev))

			return 0x0000000A;

	default:

		return 0x00000000; /* No ucode workarounds enabled */

	}
@@ -2301,18 +2276,8 @@ static void _set_ordinals(struct adreno_device *adreno_dev, 
	/* Enabled ordinal mask */

	*cmds++ = CP_INIT_MASK;



	if (CP_INIT_MASK & CP_INIT_MAX_CONTEXT) {

		/*

		 * Multiple HW ctxs are unreliable on a530v1,

		 * use single hw context.

		 * Use multiple contexts if bit set, otherwise serialize:

		 *      3D (bit 0) 2D (bit 1)

		 */

		if (adreno_is_a530v1(adreno_dev))

			*cmds++ = 0x00000000;

		else

	if (CP_INIT_MASK & CP_INIT_MAX_CONTEXT)

		*cmds++ = 0x00000003;

	}



	if (CP_INIT_MASK & CP_INIT_ERROR_DETECTION_CONTROL)

		*cmds++ = 0x20000000;

drivers/gpu/msm/adreno_a5xx_snapshot.c

+2 −12
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.

 */



#include <linux/io.h>
@@ -857,7 +857,7 @@ void a5xx_snapshot(struct adreno_device *adreno_dev, 
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct adreno_snapshot_data *snap_data = gpudev->snapshot_data;

	unsigned int reg, i;

	unsigned int i;

	struct adreno_ringbuffer *rb;

	struct registers regs;
@@ -910,16 +910,6 @@ void a5xx_snapshot(struct adreno_device *adreno_dev, 
		A5XX_CP_DRAW_STATE_ADDR, A5XX_CP_DRAW_STATE_DATA,

		0, 1 << A5XX_CP_DRAW_STATE_ADDR_WIDTH);



	/*

	 * CP needs to be halted on a530v1 before reading CP_PFP_UCODE_DBG_DATA

	 * and CP_PM4_UCODE_DBG_DATA registers

	 */

	if (adreno_is_a530v1(adreno_dev)) {

		adreno_readreg(adreno_dev, ADRENO_REG_CP_ME_CNTL, &reg);

		reg |= (1 << 27) | (1 << 28);

		adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, reg);

	}



	/* ME_UCODE Cache */

	kgsl_snapshot_indexed_registers(device, snapshot,

		A5XX_CP_ME_UCODE_DBG_ADDR, A5XX_CP_ME_UCODE_DBG_DATA,