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Commit 7690154b authored by Aditya Bavanari's avatar Aditya Bavanari Committed by Gerrit - the friendly Code Review server
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asoc: codecs: Do not update VA clk muxsel register 



Because of a HW limitation in DSP, while switching
RCG from TX MCLK to VA MCLK for SVA use cases
a glitch is seen on AHB bus leading to data
corruption in registers.
So, while doing a mux switch for VA RCG clock selection,
do not configure the muxsel register in HLOS as it is
taken care in DSP itself as a workaround for HW limitation.

Change-Id: Iccbe714397796259fa55f9852ece387e949b12e8
Signed-off-by: default avatarAditya Bavanari <abavanar@codeaurora.org>
parent 1542965d

asoc/codecs/bolero/bolero-clk-rsc.c

+44 −19
Original line number Original line Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

// SPDX-License-Identifier: GPL-2.0-only

/*

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 */

 */





#include <linux/of_platform.h>

#include <linux/of_platform.h>
@@ -250,10 +250,13 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, 




	if (enable) {

	if (enable) {

		if (priv->clk_cnt[clk_id] == 0) {

		if (priv->clk_cnt[clk_id] == 0) {

			ret = bolero_clk_rsc_mux0_clk_request(priv, default_clk_id,

			if (clk_id != VA_CORE_CLK) {

				ret = bolero_clk_rsc_mux0_clk_request(priv,

								default_clk_id,

								true);

								true);

				if (ret < 0)

				if (ret < 0)

					goto done;

					goto done;

			}





			ret = clk_prepare_enable(priv->clk[clk_id]);

			ret = clk_prepare_enable(priv->clk[clk_id]);

			if (ret < 0) {

			if (ret < 0) {
@@ -271,13 +274,23 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, 
					goto err_npl_clk;

					goto err_npl_clk;

				}

				}

			}

			}



			/*

			 * Temp SW workaround to address a glitch issue of

			 * VA GFMux instance responsible for switching from

			 * TX MCLK to VA MCLK. This configuration would be taken

			 * care in DSP itself

			 */

			if (clk_id != VA_CORE_CLK) {

				iowrite32(0x1, clk_muxsel);

				iowrite32(0x1, clk_muxsel);

				muxsel = ioread32(clk_muxsel);

				muxsel = ioread32(clk_muxsel);

				trace_printk("%s: muxsel value after enable: %d\n",

				trace_printk("%s: muxsel value after enable: %d\n",

						__func__, muxsel);

						__func__, muxsel);

			bolero_clk_rsc_mux0_clk_request(priv, default_clk_id,

				bolero_clk_rsc_mux0_clk_request(priv,

							default_clk_id,

							false);

							false);

			}

			}

		}

		priv->clk_cnt[clk_id]++;

		priv->clk_cnt[clk_id]++;

	} else {

	} else {

		if (priv->clk_cnt[clk_id] <= 0) {

		if (priv->clk_cnt[clk_id] <= 0) {
@@ -288,31 +301,43 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, 
		}

		}

		priv->clk_cnt[clk_id]--;

		priv->clk_cnt[clk_id]--;

		if (priv->clk_cnt[clk_id] == 0) {

		if (priv->clk_cnt[clk_id] == 0) {

			if (clk_id != VA_CORE_CLK) {

				ret = bolero_clk_rsc_mux0_clk_request(priv,

				ret = bolero_clk_rsc_mux0_clk_request(priv,

						default_clk_id, true);

						default_clk_id, true);





			if (!ret)

				if (!ret) {

					/*

					 * Temp SW workaround to address a glitch issue

					 * of VA GFMux instance responsible for

					 * switching from TX MCLK to VA MCLK.

					 * This configuration would be taken

					 * care in DSP itself.

					 */

					iowrite32(0x0, clk_muxsel);

					iowrite32(0x0, clk_muxsel);



					muxsel = ioread32(clk_muxsel);

					muxsel = ioread32(clk_muxsel);

					trace_printk("%s: muxsel value after disable: %d\n",

					trace_printk("%s: muxsel value after disable: %d\n",

							__func__, muxsel);

							__func__, muxsel);

				}

			}

			if (priv->clk[clk_id + NPL_CLK_OFFSET])

			if (priv->clk[clk_id + NPL_CLK_OFFSET])

				clk_disable_unprepare(

				clk_disable_unprepare(

					priv->clk[clk_id + NPL_CLK_OFFSET]);

					priv->clk[clk_id + NPL_CLK_OFFSET]);

			clk_disable_unprepare(priv->clk[clk_id]);

			clk_disable_unprepare(priv->clk[clk_id]);





			if (clk_id != VA_CORE_CLK) {

				if (!ret)

				if (!ret)

					bolero_clk_rsc_mux0_clk_request(priv,

					bolero_clk_rsc_mux0_clk_request(priv,

						default_clk_id, false);

						default_clk_id, false);

			}

			}

		}

		}

	}

	return ret;

	return ret;





err_npl_clk:

err_npl_clk:

	clk_disable_unprepare(priv->clk[clk_id]);

	clk_disable_unprepare(priv->clk[clk_id]);





err_clk:

err_clk:

	if (clk_id != VA_CORE_CLK)

		bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false);

		bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false);

done:

done:

	return ret;

	return ret;