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Commit 1542965d authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ASoC: Remove glitch during amic record"

parents 70112464 95725721

asoc/codecs/bolero/tx-macro.c

+24 −15
Original line number Diff line number Diff line
@@ -885,13 +885,14 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
	case SND_SOC_DAPM_POST_PMU:

		snd_soc_component_update_bits(component,

			tx_vol_ctl_reg, 0x20, 0x20);

		if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) {

			snd_soc_component_update_bits(component,

				hpf_gate_reg, 0x01, 0x00);

			/*

		 	 * Minimum 1 clk cycle delay is required as per HW spec

		 	 */

			usleep_range(1000, 1010);



		}

		hpf_cut_off_freq = (

			snd_soc_component_read32(component, dec_cfg_reg) &

				TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
@@ -919,15 +920,17 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				&tx_priv->tx_hpf_work[decimator].dwork,

				msecs_to_jiffies(hpf_delay));

			snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x03, 0x03);

					hpf_gate_reg, 0x03, 0x02);

			if (!(is_amic_enabled(component, decimator)

				< BOLERO_ADC_MAX))

				snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x03, 0x00);

			/*

			 * Minimum 1 clk cycle delay is required as per HW spec

			 */

			usleep_range(1000, 1010);

			snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x02, 0x00);

			snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x01, 0x01);

					hpf_gate_reg, 0x03, 0x01);

			/*

			 * 6ms delay is required as per HW spec

			 */
@@ -959,9 +962,15 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
						component, dec_cfg_reg,

						TX_HPF_CUT_OFF_FREQ_MASK,

						hpf_cut_off_freq << 5);

				if (is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)

					snd_soc_component_update_bits(component,

							hpf_gate_reg,

						0x02, 0x02);

							0x03, 0x02);

				else

					snd_soc_component_update_bits(component,

							hpf_gate_reg,

							0x03, 0x03);



				/*

				 * Minimum 1 clk cycle delay is required

				 * as per HW spec
@@ -969,7 +978,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				usleep_range(1000, 1010);

				snd_soc_component_update_bits(component,

						hpf_gate_reg,

						0x02, 0x00);

						0x03, 0x01);

			}

		}

		cancel_delayed_work_sync(

asoc/codecs/bolero/va-macro.c

+21 −13
Original line number Diff line number Diff line
@@ -1125,13 +1125,14 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
		/* Enable TX CLK */

		snd_soc_component_update_bits(component,

				tx_vol_ctl_reg, 0x20, 0x20);

		if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) {

			snd_soc_component_update_bits(component,

				hpf_gate_reg, 0x01, 0x00);

			/*

		 	 * Minimum 1 clk cycle delay is required as per HW spec

		 	 */

			usleep_range(1000, 1010);



		}

		hpf_cut_off_freq = (snd_soc_component_read32(

					component, dec_cfg_reg) &

				   TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
@@ -1150,15 +1151,16 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				va_tx_unmute_delay = unmute_delay;

		}

		snd_soc_component_update_bits(component,

				hpf_gate_reg, 0x03, 0x03);

				hpf_gate_reg, 0x03, 0x02);

		if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX))

			snd_soc_component_update_bits(component,

				hpf_gate_reg, 0x03, 0x00);

		/*

		 * Minimum 1 clk cycle delay is required as per HW spec

		 */

		usleep_range(1000, 1010);

		snd_soc_component_update_bits(component,

			hpf_gate_reg, 0x02, 0x00);

		snd_soc_component_update_bits(component,

			hpf_gate_reg, 0x01, 0x01);

			hpf_gate_reg, 0x03, 0x01);

		/*

		 * 6ms delay is required as per HW spec

		 */
@@ -1187,9 +1189,15 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
						dec_cfg_reg,

						TX_HPF_CUT_OFF_FREQ_MASK,

						hpf_cut_off_freq << 5);

				if (is_amic_enabled(component, decimator) <

					BOLERO_ADC_MAX)

					snd_soc_component_update_bits(component,

						hpf_gate_reg,

						0x02, 0x02);

						0x03, 0x02);

				else

					snd_soc_component_update_bits(component,

						hpf_gate_reg,

						0x03, 0x03);

				/*

				 * Minimum 1 clk cycle delay is required

				 * as per HW spec
@@ -1197,7 +1205,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				usleep_range(1000, 1010);

				snd_soc_component_update_bits(component,

						hpf_gate_reg,

						0x02, 0x00);

						0x03, 0x01);

			}

		}

		cancel_delayed_work_sync(