disp: msm: dsi: Update pll delay calculation as per latest DSI HPG

As per DSI HPG, pll delay should be 25usec for phy ver 4.0 and
100usec for phy ver 2.0 and 3.0. This change updates pll delay
calculation during dynamic DSI clock switch accordingly.

Change-Id: Ief5cbdc9304cf5ad025fe3bbe689b93834a1f710
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>