Merge "ARM: dts: msm: add resolution switch for qsync panel" (750b0ab2) · Commits · e / devices / android_kernel_fairphone_FP4

qcom/dsi-panel-sharp-qsync-wqhd-cmd.dtsi

+106 −0

Original line number	Diff line number	Diff line
		@@ -49,6 +49,14 @@
		qcom,mdss-dsi-v-pulse-width = <2>;
		qcom,mdss-dsi-panel-framerate = <60>;
		qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
		qcom,mdss-dsi-timing-switch-command = [
		39 01 00 00 00 00 02 ff 10
		39 01 00 00 00 00 02 fb 01
		39 01 00 00 00 00 02 c0 83
		39 01 00 00 00 00 11 c1 89 28 00 08 02
		00 02 68 00 d5 00 0a 0d b7 09 89
		39 01 00 00 00 00 03 c2 10 f0
		];
		qcom,mdss-dsi-on-command = [
		39 01 00 00 00 00 02 ff d0
		39 01 00 00 00 00 02 75 40
		@@ -125,6 +133,104 @@
		qcom,mdss-dsc-bit-per-pixel = <8>;
		qcom,mdss-dsc-block-prediction-enable;
		};

		timing@1 {
		qcom,mdss-dsi-panel-width = <540>;
		qcom,mdss-dsi-panel-height = <1920>;
		qcom,mdss-dsi-h-front-porch = <20>;
		qcom,mdss-dsi-h-back-porch = <12>;
		qcom,mdss-dsi-h-pulse-width = <8>;
		qcom,mdss-dsi-h-sync-skew = <0>;
		qcom,mdss-dsi-v-back-porch = <14>;
		qcom,mdss-dsi-v-front-porch = <16>;
		qcom,mdss-dsi-v-pulse-width = <2>;
		qcom,mdss-dsi-panel-framerate = <60>;
		qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
		qcom,mdss-dsi-timing-switch-command = [
		39 01 00 00 00 00 02 ff 10
		39 01 00 00 00 00 02 fb 01
		39 01 00 00 00 00 02 c0 85
		39 01 00 00 00 00 11 c1 89 28 00 08 02
		00 02 0e 00 bb 00 07 0d b7 0c b7
		39 01 00 00 00 00 03 c2 10 f0
		];
		qcom,mdss-dsi-on-command = [
		39 01 00 00 00 00 02 ff d0
		39 01 00 00 00 00 02 75 40
		39 01 00 00 10 00 02 f1 40
		39 01 00 00 00 00 02 ff 10
		39 01 00 00 10 00 06 2c 01 02 04 08 10
		39 01 00 00 00 00 02 ff d0
		39 01 00 00 00 00 02 75 00
		39 01 00 00 10 00 02 f1 00
		/* Initial Setting */
		39 01 00 00 00 00 02 ff 10
		39 01 00 00 00 00 02 fb 01
		39 01 00 00 00 00 02 ba 03
		39 01 00 00 00 00 02 bc 08
		39 01 00 00 00 00 02 c0 85
		39 01 00 00 00 00 11 c1 89 28 00 08 02
		00 02 0e 00 bb 00 07 0d b7 0c b7
		39 01 00 00 00 00 03 c2 10 f0
		39 01 00 00 00 00 02 d5 00
		39 01 00 00 00 00 02 d6 00
		39 01 00 00 00 00 02 de 00
		39 01 00 00 00 00 02 e1 00
		39 01 00 00 00 00 02 e5 01
		39 01 00 00 00 00 02 bb 10
		39 01 00 00 00 00 02 f6 70
		39 01 00 00 00 00 02 f7 80
		39 01 00 00 00 00 02 35 00
		39 01 00 00 00 00 02 44 00
		39 01 00 00 00 00 02 ff 20
		39 01 00 00 00 00 02 fb 01
		39 01 00 00 00 00 02 87 02
		39 01 00 00 00 00 02 5d 00
		39 01 00 00 00 00 02 5e 14
		39 01 00 00 00 00 02 5f eb
		39 01 00 00 00 00 02 ff 24
		39 01 00 00 00 00 02 fb 01
		39 01 00 00 00 00 02 14 00
		39 01 00 00 00 00 02 15 10
		39 01 00 00 00 00 02 16 00
		39 01 00 00 00 00 02 17 10
		39 01 00 00 00 00 02 ff 26
		39 01 00 00 00 00 02 fb 01
		39 01 00 00 00 00 02 60 00
		39 01 00 00 00 00 02 62 01
		39 01 00 00 00 00 02 40 00
		39 01 00 00 00 00 02 ff 28
		39 01 00 00 00 00 02 fb 01
		39 01 00 00 00 00 02 91 02
		39 01 00 00 00 00 02 ff e0
		39 01 00 00 00 00 02 fb 01
		39 01 00 00 00 00 02 48 81
		39 01 00 00 00 00 02 8e 09
		39 01 00 00 00 00 02 ff f0
		39 01 00 00 00 00 02 fb 01
		39 01 00 00 00 00 02 33 20
		39 01 00 00 00 00 02 34 35
		39 01 00 00 00 00 02 ff 10
		05 01 00 00 78 00 01 11
		05 01 00 00 78 00 01 29
		];
		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
		qcom,mdss-dsi-off-command = [
		15 01 00 00 00 00 02 ff 10
		15 01 00 00 00 00 02 bc 00
		05 01 00 00 10 00 01 28
		05 01 00 00 32 00 01 10
		];
		qcom,mdss-dsi-off-command-state = "dsi_lp_mode";

		qcom,compression-mode = "dsc";
		qcom,mdss-dsc-slice-height = <8>;
		qcom,mdss-dsc-slice-width = <540>;
		qcom,mdss-dsc-slice-per-pkt = <1>;
		qcom,mdss-dsc-bit-per-component = <8>;
		qcom,mdss-dsc-bit-per-pixel = <8>;
		qcom,mdss-dsc-block-prediction-enable;
		};
		};
		};
		};

qcom/kona-sde-display.dtsi

+60 −5

Original line number	Diff line number	Diff line
		@@ -150,10 +150,23 @@

		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
		<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
		<&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
		<&mdss_dsi0_pll PCLK_SRC_0_CLK>,
		<&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,
		<&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>,
		<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
		<&mdss_dsi1_pll PCLK_MUX_1_CLK>;
		clock-names = "src_byte_clk0", "src_pixel_clk0",
		"src_byte_clk1", "src_pixel_clk1";
		<&mdss_dsi1_pll PCLK_MUX_1_CLK>,
		<&mdss_dsi1_pll BYTECLK_SRC_1_CLK>,
		<&mdss_dsi1_pll PCLK_SRC_1_CLK>,
		<&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>,
		<&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
		"src_byte_clk0", "src_pixel_clk0",
		"shadow_byte_clk0", "shadow_pixel_clk0",
		"mux_byte_clk1", "mux_pixel_clk1",
		"src_byte_clk1", "src_pixel_clk1",
		"shadow_byte_clk1", "shadow_pixel_clk1";

		pinctrl-names = "panel_active", "panel_suspend";
		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
		@@ -181,8 +194,8 @@
		<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
		<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
		<&mdss_dsi1_pll PCLK_MUX_1_CLK>;
		clock-names = "src_byte_clk0", "src_pixel_clk0",
		"src_byte_clk1", "src_pixel_clk1";
		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
		"mux_byte_clk1", "mux_pixel_clk1";

		pinctrl-names = "panel_active", "panel_suspend";
		pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
		@@ -230,6 +243,14 @@
		qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
		qcom,mdss-dsi-panel-status-value = <0x9c>;
		qcom,mdss-dsi-panel-status-read-length = <1>;

		qcom,dsi-dyn-clk-enable;
		qcom,dsi-dyn-clk-list = <606979440 604450359 601921278>;

		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
		"src_byte_clk0", "src_pixel_clk0",
		"shadow_byte_clk0", "shadow_pixel_clk0";

		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
		@@ -254,6 +275,15 @@
		qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";
		qcom,mdss-dsi-min-refresh-rate = <55>;
		qcom,mdss-dsi-max-refresh-rate = <60>;

		qcom,dsi-dyn-clk-enable;
		qcom,dsi-dyn-clk-list =
		<534712320 532484352 530256384>;

		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
		"src_byte_clk0", "src_pixel_clk0",
		"shadow_byte_clk0", "shadow_pixel_clk0";

		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
		@@ -272,6 +302,7 @@
		qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
		qcom,mdss-dsi-panel-status-value = <0x9c>;
		qcom,mdss-dsi-panel-status-read-length = <1>;
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04
		@@ -286,6 +317,7 @@

		&dsi_sharp_4k_dsc_cmd {
		qcom,ulps-enabled;
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
		@@ -297,6 +329,7 @@
		};

		&dsi_sharp_4k_dsc_video {
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
		@@ -308,6 +341,7 @@
		};

		&dsi_sharp_qsync_wqhd_cmd {
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 1d 1c 03
		@@ -315,10 +349,18 @@
		qcom,display-topology = <2 2 2>;
		qcom,default-topology-index = <0>;
		};

		timing@1 {
		qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02
		02 00 02 04 00 0a 12];
		qcom,display-topology = <2 2 2>;
		qcom,default-topology-index = <0>;
		};
		};
		};

		&dsi_sharp_qsync_wqhd_video {
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1f 05
		@@ -331,6 +373,7 @@

		&dsi_sharp_1080_cmd {
		qcom,ulps-enabled;
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08
		@@ -344,6 +387,7 @@

		&dsi_dual_nt35597_truly_cmd {
		qcom,ulps-enabled;
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		@@ -356,6 +400,7 @@
		};

		&dsi_dual_nt35597_truly_video {
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-min-refresh-rate = <53>;
		qcom,mdss-dsi-max-refresh-rate = <60>;
		qcom,mdss-dsi-pan-enable-dynamic-fps;
		@@ -373,6 +418,7 @@

		&dsi_nt35695b_truly_fhd_cmd {
		qcom,ulps-enabled;
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
		@@ -384,6 +430,7 @@
		};

		&dsi_nt35695b_truly_fhd_video {
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
		@@ -396,6 +443,7 @@

		&dsi_sim_cmd {
		qcom,ulps-enabled;
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		@@ -446,6 +494,7 @@
		};

		&dsi_sim_vid {
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		@@ -459,6 +508,7 @@

		&dsi_sim_dsc_375_cmd {
		qcom,ulps-enabled;
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 { /* 1080p */
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		@@ -480,6 +530,7 @@

		&dsi_sim_dsc_10b_cmd {
		qcom,ulps-enabled;
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 { /* QHD 60fps */
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		@@ -508,6 +559,7 @@

		&dsi_dual_sim_cmd {
		qcom,ulps-enabled;
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
		@@ -534,6 +586,7 @@
		};

		&dsi_dual_sim_vid {
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		@@ -547,6 +600,7 @@

		&dsi_dual_sim_dsc_375_cmd {
		qcom,ulps-enabled;
		qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
		qcom,mdss-dsi-display-timings {
		timing@0 { /* qhd */
		qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
		@@ -573,6 +627,7 @@

		&dsi_sim_sec_hd_cmd {
		qcom,ulps-enabled;
		qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1";
		qcom,mdss-dsi-display-timings {
		timing@0 {
		qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22

qcom/kona-sde-pll.dtsi

+9 −4

Original line number	Diff line number	Diff line
		@@ -6,11 +6,14 @@
		#clock-cells = <1>;
		reg = <0xae94900 0x260>,
		<0xae94400 0x800>,
		<0xaf03000 0x8>;
		reg-names = "pll_base", "phy_base", "gdsc_base";
		<0xaf03000 0x8>,
		<0xae94200 0x100>;
		reg-names = "pll_base", "phy_base", "gdsc_base",
		"dynamic_pll_base";
		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
		clock-names = "iface_clk";
		clock-rate = <0>;
		memory-region = <&dfps_data_memory>;
		gdsc-supply = <&mdss_core_gdsc>;
		qcom,dsi-pll-ssc-en;
		qcom,dsi-pll-ssc-mode = "down-spread";
		@@ -35,8 +38,10 @@
		#clock-cells = <1>;
		reg = <0xae96900 0x260>,
		<0xae96400 0x800>,
		<0xaf03000 0x8>;
		reg-names = "pll_base", "phy_base", "gdsc_base";
		<0xaf03000 0x8>,
		<0xae96200 0x100>;
		reg-names = "pll_base", "phy_base", "gdsc_base",
		"dynamic_pll_base";
		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
		clock-names = "iface_clk";
		clock-rate = <0>;

qcom/kona-sde.dtsi

+6 −4

Original line number	Diff line number	Diff line
		@@ -623,8 +623,9 @@
		compatible = "qcom,dsi-phy-v4.1";
		label = "dsi-phy-0";
		cell-index = <0>;
		reg = <0xae94400 0x760>;
		reg-names = "dsi_phy";
		reg = <0xae94400 0x7c0>,
		<0xae94200 0x100>;
		reg-names = "dsi_phy", "dyn_refresh_base";
		vdda-0p9-supply = <&pm8150_l5>;
		qcom,platform-strength-ctrl = [55 03
		55 03
		@@ -655,8 +656,9 @@
		compatible = "qcom,dsi-phy-v4.1";
		label = "dsi-phy-1";
		cell-index = <1>;
		reg = <0xae96400 0x760>;
		reg-names = "dsi_phy";
		reg = <0xae96400 0x7c0>,
		<0xae96200 0x100>;
		reg-names = "dsi_phy", "dyn_refresh_base";
		vdda-0p9-supply = <&pm8150_l5>;
		qcom,platform-strength-ctrl = [55 03
		55 03

qcom/kona.dtsi

+6 −1

Original line number	Diff line number	Diff line
		@@ -607,7 +607,7 @@
		};

		cont_splash_memory: cont_splash_region@9c000000 {
		reg = <0x0 0x9c000000 0x0 0x02400000>;
		reg = <0x0 0x9c000000 0x0 0x02300000>;
		label = "cont_splash_region";
		};

		@@ -616,6 +616,11 @@
		label = "disp_rdump_region";
		};

		dfps_data_memory: dfps_data_region@9e300000 {
		reg = <0x0 0x9e300000 0x0 0x0100000>;
		label = "dfps_data_region";
		};

		dump_mem: mem_dump_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;