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Commit 7157c69a authored by Alex Frid's avatar Alex Frid Committed by Stephen Boyd
Browse files

clk: tegra: Fix Tegra210 PLLU initialization 



- Added necessary delays in PLLU enable sequence during initialization
- Applied PLLU lock to all secondary gates (PLLU_48M and PLLU_60M were
missing).

Signed-off-by: default avatarAlex Frid <afrid@nvidia.com>
Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 71422dbb

drivers/clk/tegra/clk-tegra210.c

+4 −2
Original line number Diff line number Diff line
@@ -2554,6 +2554,7 @@ static int tegra210_enable_pllu(void) 
	reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);

	reg &= ~BIT(pllu.params->iddq_bit_idx);

	writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);

	udelay(5);



	reg = readl_relaxed(clk_base + PLLU_BASE);

	reg &= ~GENMASK(20, 0);
@@ -2561,6 +2562,7 @@ static int tegra210_enable_pllu(void) 
	reg |= fentry->n << 8;

	reg |= fentry->p << 16;

	writel(reg, clk_base + PLLU_BASE);

	udelay(1);

	reg |= PLL_ENABLE;

	writel(reg, clk_base + PLLU_BASE);
@@ -2800,14 +2802,14 @@ static void __init tegra210_pll_init(void __iomem *clk_base, 
	/* PLLU_60M */

	clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",

				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,

				23, 0, NULL);

				23, 0, &pll_u_lock);

	clk_register_clkdev(clk, "pll_u_60M", NULL);

	clks[TEGRA210_CLK_PLL_U_60M] = clk;



	/* PLLU_48M */

	clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",

				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,

				25, 0, NULL);

				25, 0, &pll_u_lock);

	clk_register_clkdev(clk, "pll_u_48M", NULL);

	clks[TEGRA210_CLK_PLL_U_48M] = clk;