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Commit 7064f601 authored by Robin Gong's avatar Robin Gong Committed by Sasha Levin
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regualtor: pfuze100: correct sw1a/sw2 on pfuze3000 



[ Upstream commit 6f1cf5257acc6e6242ddf2f52bc7912aed77b79f ]

PFUZE100_SWB_REG is not proper for sw1a/sw2, because enable_mask/enable_reg
is not correct. On PFUZE3000, sw1a/sw2 should be the same as sw1a/sw2 on
pfuze100 except that voltages are not linear, so add new PFUZE3000_SW_REG
and pfuze3000_sw_regulator_ops which like the non-linear PFUZE100_SW_REG
and pfuze100_sw_regulator_ops.

Fixes: 1dced996 ("regulator: pfuze100: update voltage setting for pfuze3000 sw1a")
Reported-by: default avatarChristophe Meynard <Christophe.Meynard@ign.fr>
Signed-off-by: default avatarRobin Gong <yibin.gong@nxp.com>
Link: https://lore.kernel.org/r/1592171648-8752-1-git-send-email-yibin.gong@nxp.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent a717bbd1

drivers/regulator/pfuze100-regulator.c

+39 −21
Original line number Diff line number Diff line
@@ -196,6 +196,19 @@ static const struct regulator_ops pfuze100_swb_regulator_ops = { 


};



static const struct regulator_ops pfuze3000_sw_regulator_ops = {

	.enable = regulator_enable_regmap,

	.disable = regulator_disable_regmap,

	.is_enabled = regulator_is_enabled_regmap,

	.list_voltage = regulator_list_voltage_table,

	.map_voltage = regulator_map_voltage_ascend,

	.set_voltage_sel = regulator_set_voltage_sel_regmap,

	.get_voltage_sel = regulator_get_voltage_sel_regmap,

	.set_voltage_time_sel = regulator_set_voltage_time_sel,

	.set_ramp_delay = pfuze100_set_ramp_delay,



};



#define PFUZE100_FIXED_REG(_chip, _name, base, voltage)	\

	[_chip ## _ ## _name] = {	\

		.desc = {	\
@@ -305,22 +318,27 @@ static const struct regulator_ops pfuze100_swb_regulator_ops = { 
	.stby_mask = 0x20,	\

}





#define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step)	{	\

/* No linar case for the some switches of PFUZE3000 */

#define PFUZE3000_SW_REG(_chip, _name, base, mask, voltages)	\

	[_chip ## _ ##  _name] = {	\

		.desc = {	\

			.name = #_name,	\

		.n_voltages = ((max) - (min)) / (step) + 1,	\

		.ops = &pfuze100_sw_regulator_ops,	\

			.n_voltages = ARRAY_SIZE(voltages),	\

			.ops = &pfuze3000_sw_regulator_ops,	\

			.type = REGULATOR_VOLTAGE,	\

			.id = _chip ## _ ## _name,	\

			.owner = THIS_MODULE,	\

		.min_uV = (min),	\

		.uV_step = (step),	\

			.volt_table = voltages,	\

			.vsel_reg = (base) + PFUZE100_VOL_OFFSET,	\

		.vsel_mask = 0x7,	\

			.vsel_mask = (mask),	\

			.enable_reg = (base) + PFUZE100_MODE_OFFSET,	\

			.enable_mask = 0xf,	\

			.enable_val = 0x8,	\

			.enable_time = 500,	\

		},	\

		.stby_reg = (base) + PFUZE100_STANDBY_OFFSET,	\

	.stby_mask = 0x7,	\

		.stby_mask = (mask),	\

		.sw_reg = true,		\

	}



#define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step)	{	\
@@ -377,9 +395,9 @@ static struct pfuze_regulator pfuze200_regulators[] = { 
};



static struct pfuze_regulator pfuze3000_regulators[] = {

	PFUZE100_SWB_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),

	PFUZE3000_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),

	PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),

	PFUZE100_SWB_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),

	PFUZE3000_SW_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),

	PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),

	PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),

	PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
@@ -393,8 +411,8 @@ static struct pfuze_regulator pfuze3000_regulators[] = { 
};



static struct pfuze_regulator pfuze3001_regulators[] = {

	PFUZE100_SWB_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),

	PFUZE100_SWB_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),

	PFUZE3000_SW_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),

	PFUZE3000_SW_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),

	PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),

	PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),

	PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),