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Commit 6f942345 authored by Kevin Cernekee's avatar Kevin Cernekee Committed by John Crispin
Browse files

MIPS: BCM63XX: Add new IUDMA definitions needed for USBD 



Signed-off-by: default avatarKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4083/


Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
parent 932e30b6

arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -11,6 +11,7 @@ struct bcm_enet_desc { 
	u32 address;

	u32 address;

};

};





/* control */

#define DMADESC_LENGTH_SHIFT	16

#define DMADESC_LENGTH_SHIFT	16

#define DMADESC_LENGTH_MASK	(0xfff << DMADESC_LENGTH_SHIFT)

#define DMADESC_LENGTH_MASK	(0xfff << DMADESC_LENGTH_SHIFT)

#define DMADESC_OWNER_MASK	(1 << 15)

#define DMADESC_OWNER_MASK	(1 << 15)
@@ -18,7 +19,10 @@ struct bcm_enet_desc { 
#define DMADESC_SOP_MASK	(1 << 13)

#define DMADESC_SOP_MASK	(1 << 13)

#define DMADESC_ESOP_MASK	(DMADESC_EOP_MASK | DMADESC_SOP_MASK)

#define DMADESC_ESOP_MASK	(DMADESC_EOP_MASK | DMADESC_SOP_MASK)

#define DMADESC_WRAP_MASK	(1 << 12)

#define DMADESC_WRAP_MASK	(1 << 12)

#define DMADESC_USB_NOZERO_MASK	(1 << 1)

#define DMADESC_USB_ZERO_MASK	(1 << 0)





/* status */

#define DMADESC_UNDER_MASK	(1 << 9)

#define DMADESC_UNDER_MASK	(1 << 9)

#define DMADESC_APPEND_CRC	(1 << 8)

#define DMADESC_APPEND_CRC	(1 << 8)

#define DMADESC_OVSIZE_MASK	(1 << 4)

#define DMADESC_OVSIZE_MASK	(1 << 4)

arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h

+10 −2
Original line number Original line Diff line number Diff line
@@ -670,6 +670,12 @@ 
#define ENETDMA_BUFALLOC_FORCE_SHIFT	31

#define ENETDMA_BUFALLOC_FORCE_SHIFT	31

#define ENETDMA_BUFALLOC_FORCE_MASK	(1 << ENETDMA_BUFALLOC_FORCE_SHIFT)

#define ENETDMA_BUFALLOC_FORCE_MASK	(1 << ENETDMA_BUFALLOC_FORCE_SHIFT)





/* Global interrupt status */

#define ENETDMA_GLB_IRQSTAT_REG		(0x40)



/* Global interrupt mask */

#define ENETDMA_GLB_IRQMASK_REG		(0x44)



/* Channel Configuration register */

/* Channel Configuration register */

#define ENETDMA_CHANCFG_REG(x)		(0x100 + (x) * 0x10)

#define ENETDMA_CHANCFG_REG(x)		(0x100 + (x) * 0x10)

#define ENETDMA_CHANCFG_EN_SHIFT	0

#define ENETDMA_CHANCFG_EN_SHIFT	0
@@ -709,9 +715,11 @@ 
/* Channel Configuration register */

/* Channel Configuration register */

#define ENETDMAC_CHANCFG_REG(x)		((x) * 0x10)

#define ENETDMAC_CHANCFG_REG(x)		((x) * 0x10)

#define ENETDMAC_CHANCFG_EN_SHIFT	0

#define ENETDMAC_CHANCFG_EN_SHIFT	0

#define ENETDMAC_CHANCFG_EN_MASK	(1 << ENETDMA_CHANCFG_EN_SHIFT)

#define ENETDMAC_CHANCFG_EN_MASK	(1 << ENETDMAC_CHANCFG_EN_SHIFT)

#define ENETDMAC_CHANCFG_PKTHALT_SHIFT	1

#define ENETDMAC_CHANCFG_PKTHALT_SHIFT	1

#define ENETDMAC_CHANCFG_PKTHALT_MASK	(1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)

#define ENETDMAC_CHANCFG_PKTHALT_MASK	(1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)

#define ENETDMAC_CHANCFG_BUFHALT_SHIFT	2

#define ENETDMAC_CHANCFG_BUFHALT_MASK	(1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)





/* Interrupt Control/Status register */

/* Interrupt Control/Status register */

#define ENETDMAC_IR_REG(x)		(0x4 + (x) * 0x10)

#define ENETDMAC_IR_REG(x)		(0x4 + (x) * 0x10)