Loading msm/sde/sde_hw_catalog.c +2 −2 Original line number Diff line number Diff line Loading @@ -4295,7 +4295,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->has_cwb_support = true; sde_cfg->has_wb_ubwc = true; sde_cfg->has_qsync = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->perf.min_prefill_lines = 35; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; Loading Loading @@ -4345,7 +4345,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) } else if (IS_LAGOON_TARGET(hw_rev)) { sde_cfg->has_cwb_support = true; sde_cfg->has_qsync = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->perf.min_prefill_lines = 35; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; Loading Loading
msm/sde/sde_hw_catalog.c +2 −2 Original line number Diff line number Diff line Loading @@ -4295,7 +4295,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->has_cwb_support = true; sde_cfg->has_wb_ubwc = true; sde_cfg->has_qsync = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->perf.min_prefill_lines = 35; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; Loading Loading @@ -4345,7 +4345,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) } else if (IS_LAGOON_TARGET(hw_rev)) { sde_cfg->has_cwb_support = true; sde_cfg->has_qsync = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->perf.min_prefill_lines = 35; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; Loading