Merge "clk: qcom: gcc-lito: update dfs clocks to correctly use new macro" (6f232f58) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/clk/qcom/gcc-lito.c

+39 −39

Original line number	Diff line number	Diff line
		@@ -374,7 +374,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
		},
		};

		static struct clk_init_data gcc_npu_dma_clk_init = {
		static struct clk_init_data gcc_npu_dma_clk_src_init = {
		.name = "gcc_npu_dma_clk_src",
		.parent_names = gcc_parent_names_3,
		.num_parents = 7,
		@@ -394,7 +394,7 @@ static struct clk_rcg2 gcc_npu_dma_clk_src = {
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gcc_parent_map_3,
		.clkr.hw.init = &gcc_npu_dma_clk_init,
		.clkr.hw.init = &gcc_npu_dma_clk_src_init,
		};

		static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
		@@ -444,7 +444,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
		{ }
		};

		static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s0_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -463,10 +463,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
		};

		static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s1_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -485,10 +485,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
		};

		static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s2_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -507,10 +507,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
		};

		static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s3_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -529,10 +529,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
		};

		static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s4_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -551,10 +551,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
		};

		static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s5_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -573,10 +573,10 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
		};

		static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s0_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -595,10 +595,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
		};

		static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s1_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -617,10 +617,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
		};

		static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s2_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -639,10 +639,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
		};

		static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s3_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -661,10 +661,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
		};

		static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s4_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -683,10 +683,10 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
		};

		static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = {
		static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s5_clk_src",
		.parent_names = gcc_parent_names_0,
		.num_parents = 4,
		@@ -705,7 +705,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_0,
		.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
		.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init,
		.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
		};

		static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
		@@ -2699,19 +2699,19 @@ static const struct qcom_reset_map gcc_lito_resets[] = {
		};

		static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
		DEFINE_RCG_DFS(gcc_npu_dma_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk),
		DEFINE_RCG_DFS(gcc_npu_dma_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
		DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
		};

		static const struct regmap_config gcc_lito_regmap_config = {