coresight: tmc: Change ETR DDR transaction configuration

Set AXI control register on ETR to use normal non-cacheable
bufferable mode to meet bandwidth requirement. There is a
disconnect between the AXI protocol version on ETR versus the
rest of the system. The below table illustrates the correct
config to be used
-----------------------------------------------------------------
ARCACHE[1:0] | AWCACHE[1:0] | Memorytype
          00 |           00 | Device Non-bufferable
          01 |           01 | Device Bufferable
          10 |           10 | Normal Non-cacheable Non-bufferable
          11 |           11 | Normal Non-cacheable Bufferable
----------------------------------------------------------------

Change-Id: I0c2255389641ede80702415b4083bfc9a46881be
Signed-off-by: Satyajit Desai <sadesai@codeaurora.org>
Signed-off-by: Rama Aparna Mallavarapu <aparnam@codeaurora.org>