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Commit 6dad6c95 authored by Seungwon Jeon's avatar Seungwon Jeon Committed by Chris Ball
Browse files

mmc: mmci: clarify DDR timing mode between SD-UHS and eMMC 



Added MMC_DDR52 as eMMC's DDR mode distinguished from SD-UHS.

CC: Russell King <linux@arm.linux.org.uk>
Signed-off-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarChris Ball <chris@printf.net>
parent 79f7ae7c

drivers/mmc/host/mmci.c

+4 −2
Original line number Diff line number Diff line
@@ -299,7 +299,8 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 
	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)

		clk |= MCI_ST_8BIT_BUS;



	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)

	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||

	    host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)

		clk |= MCI_ST_UX500_NEG_EDGE;



	mmci_write_clkreg(host, clk);
@@ -784,7 +785,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 
			mmci_write_clkreg(host, clk);

		}



	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)

	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||

	    host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)

		datactrl |= MCI_ST_DPSM_DDRMODE;



	/*