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Commit 79f7ae7c authored by Seungwon Jeon's avatar Seungwon Jeon Committed by Chris Ball
Browse files

mmc: clarify DDR timing mode between SD-UHS and eMMC 



This change distinguishes DDR timing mode of current
mixed usage to clarify device type.

Signed-off-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Acked-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarChris Ball <chris@printf.net>
parent a798c10f

drivers/mmc/core/debugfs.c

+3 −0
Original line number Diff line number Diff line
@@ -135,6 +135,9 @@ static int mmc_ios_show(struct seq_file *s, void *data) 
	case MMC_TIMING_UHS_DDR50:

		str = "sd uhs DDR50";

		break;

	case MMC_TIMING_MMC_DDR52:

		str = "mmc DDR52";

		break;

	case MMC_TIMING_MMC_HS200:

		str = "mmc high-speed SDR200";

		break;

drivers/mmc/core/mmc.c

+1 −1
Original line number Diff line number Diff line
@@ -1264,7 +1264,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, 
					goto err;

			}

			mmc_card_set_ddr_mode(card);

			mmc_set_timing(card->host, MMC_TIMING_UHS_DDR50);

			mmc_set_timing(card->host, MMC_TIMING_MMC_DDR52);

			mmc_set_bus_width(card->host, bus_width);

		}

	}

include/linux/mmc/host.h

+2 −1
Original line number Diff line number Diff line
@@ -58,7 +58,8 @@ struct mmc_ios { 
#define MMC_TIMING_UHS_SDR50	5

#define MMC_TIMING_UHS_SDR104	6

#define MMC_TIMING_UHS_DDR50	7

#define MMC_TIMING_MMC_HS200	8

#define MMC_TIMING_MMC_DDR52	8

#define MMC_TIMING_MMC_HS200	9



#define MMC_SDR_MODE		0

#define MMC_1_2V_DDR_MODE	1