Loading drivers/clk/qcom/clk-branch.c +65 −0 Original line number Diff line number Diff line Loading @@ -312,6 +312,71 @@ const struct clk_ops clk_branch2_ops = { }; EXPORT_SYMBOL_GPL(clk_branch2_ops); static int clk_branch2_hw_ctl_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { if (!(hw->init->flags & CLK_SET_RATE_PARENT)) { pr_err("SET_RATE_PARENT flag needs to be set for %s\n", clk_hw_get_name(hw)); return -EINVAL; } return 0; } static unsigned long clk_branch2_hw_ctl_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { return parent_rate; } static int clk_branch2_hw_ctl_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_hw *clkp; clkp = clk_hw_get_parent(hw); if (!clkp) return -EINVAL; req->best_parent_hw = clkp; req->best_parent_rate = clk_round_rate(clkp->clk, req->rate); return 0; } static int clk_branch2_hw_ctl_enable(struct clk_hw *hw) { struct clk_hw *parent = clk_hw_get_parent(hw); /* The parent branch clock should have been prepared prior to this. */ if (!parent || (parent && !clk_hw_is_prepared(parent))) return -EINVAL; return clk_enable_regmap(hw); } static void clk_branch2_hw_ctl_disable(struct clk_hw *hw) { struct clk_hw *parent = clk_hw_get_parent(hw); if (!parent) return; clk_disable_regmap(hw); } const struct clk_ops clk_branch2_hw_ctl_ops = { .enable = clk_branch2_hw_ctl_enable, .disable = clk_branch2_hw_ctl_disable, .is_enabled = clk_is_enabled_regmap, .set_rate = clk_branch2_hw_ctl_set_rate, .recalc_rate = clk_branch2_hw_ctl_recalc_rate, .determine_rate = clk_branch2_hw_ctl_determine_rate, .set_flags = clk_branch_set_flags, }; EXPORT_SYMBOL_GPL(clk_branch2_hw_ctl_ops); const struct clk_ops clk_branch_simple_ops = { .enable = clk_enable_regmap, .disable = clk_disable_regmap, Loading drivers/clk/qcom/clk-branch.h +1 −0 Original line number Diff line number Diff line Loading @@ -43,6 +43,7 @@ struct clk_branch { extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch2_hw_ctl_ops; extern const struct clk_ops clk_branch_simple_ops; #define to_clk_branch(_hw) \ Loading Loading
drivers/clk/qcom/clk-branch.c +65 −0 Original line number Diff line number Diff line Loading @@ -312,6 +312,71 @@ const struct clk_ops clk_branch2_ops = { }; EXPORT_SYMBOL_GPL(clk_branch2_ops); static int clk_branch2_hw_ctl_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { if (!(hw->init->flags & CLK_SET_RATE_PARENT)) { pr_err("SET_RATE_PARENT flag needs to be set for %s\n", clk_hw_get_name(hw)); return -EINVAL; } return 0; } static unsigned long clk_branch2_hw_ctl_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { return parent_rate; } static int clk_branch2_hw_ctl_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_hw *clkp; clkp = clk_hw_get_parent(hw); if (!clkp) return -EINVAL; req->best_parent_hw = clkp; req->best_parent_rate = clk_round_rate(clkp->clk, req->rate); return 0; } static int clk_branch2_hw_ctl_enable(struct clk_hw *hw) { struct clk_hw *parent = clk_hw_get_parent(hw); /* The parent branch clock should have been prepared prior to this. */ if (!parent || (parent && !clk_hw_is_prepared(parent))) return -EINVAL; return clk_enable_regmap(hw); } static void clk_branch2_hw_ctl_disable(struct clk_hw *hw) { struct clk_hw *parent = clk_hw_get_parent(hw); if (!parent) return; clk_disable_regmap(hw); } const struct clk_ops clk_branch2_hw_ctl_ops = { .enable = clk_branch2_hw_ctl_enable, .disable = clk_branch2_hw_ctl_disable, .is_enabled = clk_is_enabled_regmap, .set_rate = clk_branch2_hw_ctl_set_rate, .recalc_rate = clk_branch2_hw_ctl_recalc_rate, .determine_rate = clk_branch2_hw_ctl_determine_rate, .set_flags = clk_branch_set_flags, }; EXPORT_SYMBOL_GPL(clk_branch2_hw_ctl_ops); const struct clk_ops clk_branch_simple_ops = { .enable = clk_enable_regmap, .disable = clk_disable_regmap, Loading
drivers/clk/qcom/clk-branch.h +1 −0 Original line number Diff line number Diff line Loading @@ -43,6 +43,7 @@ struct clk_branch { extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch2_hw_ctl_ops; extern const struct clk_ops clk_branch_simple_ops; #define to_clk_branch(_hw) \ Loading