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Commit 68526e58 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Linus Walleij
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ARM: ux500: select L2X0 cache on ux500



The cache controller needs to be enabled for the
cortex-a9 specific errata that are also selected
to work.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent ded547a4
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