Loading arch/arm64/boot/dts/qcom/lito.dtsi +18 −0 Original line number Diff line number Diff line Loading @@ -861,6 +861,16 @@ qcom,dump-node = <&L2_TLB_700>; qcom,dump-id = <0x127>; }; qcom,llcc1_d_cache { qcom,dump-node = <&LLCC_1>; qcom,dump-id = <0x140>; }; qcom,llcc2_d_cache { qcom,dump-node = <&LLCC_2>; qcom,dump-id = <0x141>; }; }; qcom,sps { Loading Loading @@ -1222,6 +1232,14 @@ reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; cap-based-alloc-and-pwr-collapse; LLCC_1: llcc_1_dcache { qcom,dump-size = <0x1141c0>; }; LLCC_2: llcc_2_dcache { qcom,dump-size = <0x1141c0>; }; }; cpu_pmu: cpu-pmu { Loading Loading
arch/arm64/boot/dts/qcom/lito.dtsi +18 −0 Original line number Diff line number Diff line Loading @@ -861,6 +861,16 @@ qcom,dump-node = <&L2_TLB_700>; qcom,dump-id = <0x127>; }; qcom,llcc1_d_cache { qcom,dump-node = <&LLCC_1>; qcom,dump-id = <0x140>; }; qcom,llcc2_d_cache { qcom,dump-node = <&LLCC_2>; qcom,dump-id = <0x141>; }; }; qcom,sps { Loading Loading @@ -1222,6 +1232,14 @@ reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; cap-based-alloc-and-pwr-collapse; LLCC_1: llcc_1_dcache { qcom,dump-size = <0x1141c0>; }; LLCC_2: llcc_2_dcache { qcom,dump-size = <0x1141c0>; }; }; cpu_pmu: cpu-pmu { Loading