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Commit 448973a2 authored by Neeraj Upadhyay's avatar Neeraj Upadhyay Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Enable LLCC dumps for Lito 



Enable LLCC cache slice dumps for Lito SoC.

Change-Id: I8eeb9b229b3e1a8e4e5d37ab658994230d4cdb73
Signed-off-by: default avatarNeeraj Upadhyay <neeraju@codeaurora.org>
parent 7ede1bd9

arch/arm64/boot/dts/qcom/lito.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -861,6 +861,16 @@ 
			qcom,dump-node = <&L2_TLB_700>;

			qcom,dump-id = <0x127>;

		};



		qcom,llcc1_d_cache {

			qcom,dump-node = <&LLCC_1>;

			qcom,dump-id = <0x140>;

		};



		qcom,llcc2_d_cache {

			qcom,dump-node = <&LLCC_2>;

			qcom,dump-id = <0x141>;

		};

	};



	qcom,sps {
@@ -1222,6 +1232,14 @@ 
		reg-names = "llcc_base", "llcc_broadcast_base";

		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

		cap-based-alloc-and-pwr-collapse;



		LLCC_1: llcc_1_dcache {

			qcom,dump-size = <0x1141c0>;

		};



		LLCC_2: llcc_2_dcache {

			qcom,dump-size = <0x1141c0>;

		};

	};



	cpu_pmu: cpu-pmu {