Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6845d36b authored by Raghu Ananya Arabolu's avatar Raghu Ananya Arabolu
Browse files

ARM: dts: qcom: Remove GMU power levels from GPU dtsi 

The GMU power levels are now hardcoded. Remove the device node
binding that defines the set of GMU power levels.

Change-Id: Ib439f20c8c77af38b579c1222a8915231ab26b84
parent 3e9c170e

bindings/gpu/adreno-gmu.txt

+0 −28
Original line number Diff line number Diff line
@@ -41,15 +41,6 @@ GMU GDSC/regulators: 
			"gmu_clk", "ahb_clk", "cxo_clk", "axi_clk", "memnoc_clk",

			"rbcpr_clk"



- qcom,gmu-pwrlevels: device node defines a set of GMU power levels. It has

		following required properties:



		- compatible : "qcom,gmu-pwrlevels"

		- qcom,gmu-pwrlevel: a single power level. Each power level has

		  below properties:

			- reg: index of the powerlevel (0 = highest perf)

			- qcom, gmu-freq: GMU frequency for the power level in Hz.



- List of sub nodes, one for each of the translation context banks needed

		for GMU to access system memory in different operating mode. Currently

		supported names are:
@@ -98,25 +89,6 @@ gmu: qcom,gmu@2c6a000 { 
	clock-names = "gmu_clk", "ahb_clk", "cxo_clk",

				"axi_clk", "memnoc_clk", "rbcpr_clk";



	qcom,gmu-pwrlevels {



	      compatible = "qcom,gmu-pwrlevels";

	      qcom,gpu-pwrlevel@0 {

	          reg = <0>;

	          qcom,gmu-freq = <500000000>;

	      };



	      qcom,gpu-pwrlevel@1 {

	          reg = <1>;

	          qcom,gmu-freq = <200000000>;

	      };



	      qcom,gpu-pwrlevel@2 {

	          reg = <2>;

	          qcom,gmu-freq = <0>;

	      };

	};



	gmu_user: gmu_user {

	      compatible = "qcom,smmu-gmu-user-cb";

	      iommus = <&kgsl_smmu 4>;

qcom/kona-gpu.dtsi

+0 −18
Original line number Diff line number Diff line
@@ -326,24 +326,6 @@ 
		mboxes = <&qmp_aop 0>;

		mbox-names = "aop";



		qcom,gmu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible = "qcom,gmu-pwrlevels";



			/* GMU power levels must go from lowest to highest */

			qcom,gmu-pwrlevel@0 {

				reg = <0>;

				qcom,gmu-freq = <0>;

			};



			qcom,gmu-pwrlevel@1 {

				reg = <1>;

				qcom,gmu-freq = <200000000>;

			};

		};



		gmu_user: gmu_user {

			compatible = "qcom,smmu-gmu-user-cb";

			iommus = <&kgsl_smmu 0x4 0x400>;