Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3e9c170e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Add NPU support for lito"

parents 6ec2fcfc c648d019

qcom/lito-npu.dtsi

0 → 100644
+227 −0
Original line number Diff line number Diff line 
&soc {

	msm_npu: qcom,msm_npu@9800000 {

		compatible = "qcom,msm-npu";

		status = "ok";

		reg = <0x9900000 0x20000>,

			<0x99F0000 0x10000>,

			<0x9800000 0x100000>,

			<0x9980000 0x10000>,

			<0x17c00000 0x10000>;

		reg-names = "tcm", "core", "qdsp", "cc", "apss_shared";

		interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,

				<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",

					"general_irq";

		iommus = <&apps_smmu 0x1861 0x400>, <&apps_smmu 0x1862 0x400>;



		clocks = <&npucc NPU_CC_XO_CLK>,

				<&npucc NPU_CC_CORE_CLK>,

				<&npucc NPU_CC_CAL_HM0_CLK>,

				<&npucc NPU_CC_CAL_HM0_CDC_CLK>,

				<&npucc NPU_CC_NOC_AXI_CLK>,

				<&npucc NPU_CC_NOC_AHB_CLK>,

				<&npucc NPU_CC_NOC_DMA_CLK>,

				<&npucc NPU_CC_LLM_CLK>,

				<&npucc NPU_CC_LLM_XO_CLK>,

				<&npucc NPU_CC_LLM_TEMP_CLK>,

				<&npucc NPU_CC_LLM_CURR_CLK>,

				<&npucc NPU_CC_DL_LLM_CLK>,

				<&npucc NPU_CC_ISENSE_CLK>,

				<&npucc NPU_CC_DPM_CLK>,

				<&npucc NPU_CC_DPM_XO_CLK>,

				<&npucc NPU_CC_DL_DPM_CLK>,

				<&npucc NPU_CC_RSC_XO_CLK>,

				<&npucc NPU_CC_DPM_TEMP_CLK>,

				<&npucc NPU_CC_CAL_HM0_DPM_IP_CLK>,

				<&npucc NPU_CC_S2P_CLK>,

				<&npucc NPU_CC_BWMON_CLK>,

				<&npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>,

				<&npucc NPU_CC_BTO_CORE_CLK>,

				<&npucc NPU_DSP_CORE_CLK_SRC>;

		clock-names = "xo_clk",

				"npu_core_clk",

				"cal_hm0_clk",

				"cal_hm0_cdc_clk",

				"axi_clk",

				"ahb_clk",

				"dma_clk",

				"llm_clk",

				"llm_xo_clk",

				"llm_temp_clk",

				"llm_curr_clk",

				"dl_llm_clk",

				"isense_clk",

				"dpm_clk",

				"dpm_xo_clk",

				"dl_dpm_clk",

				"rsc_xo_clk",

				"dpm_temp_clk",

				"cal_hm0_dpm_ip_clk",

				"s2p_clk",

				"bwmon_clk",

				"cal_hm0_perf_cnt_clk",

				"bto_core_clk",

				"dsp_core_clk_src";



		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-reg-names ="vdd", "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		mboxes = <&qmp_aop 0>;

		mbox-names = "aop";

		#cooling-cells = <2>;

		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

		qcom,npu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,npu-pwrlevels";

			initial-pwrlevel = <4>;

			qcom,npu-pwrlevel@0 {

				reg = <0>;

				vreg = <1>;

				clk-freq = <19200000

					100000000

					300000000

					300000000

					150000000

					40000000

					300000000

					100000000

					19200000

					50000000

					50000000

					100000000

					100000000

					100000000

					19200000

					100000000

					19200000

					50000000

					300000000

					50000000

					19200000

					300000000

					19200000

					300000000>;

			};



			qcom,npu-pwrlevel@1 {

				reg = <1>;

				vreg = <2>;

				clk-freq = <19200000

					200000000

					518400000

					518400000

					207000000

					40000000

					403000000

					200000000

					19200000

					50000000

					50000000

					200000000

					200000000

					200000000

					19200000

					200000000

					19200000

					50000000

					518400000

					50000000

					19200000

					518400000

					19200000

					400000000>;

			};



			qcom,npu-pwrlevel@2 {

				reg = <2>;

				vreg = <3>;

				clk-freq = <19200000

					333000000

					633600000

					633600000

					300000000

					75000000

					533000000

					214000000

					19200000

					50000000

					100000000

					214000000

					214000000

					214000000

					19200000

					214000000

					19200000

					50000000

					633600000

					50000000

					19200000

					633600000

					19200000

					500000000>;

			};



			qcom,npu-pwrlevel@3 {

				reg = <3>;

				vreg = <4>;

				clk-freq = <19200000

					428000000

					825000000

					825000000

					403000000

					75000000

					700000000

					300000000

					19200000

					100000000

					200000000

					300000000

					300000000

					300000000

					19200000

					300000000

					19200000

					100000000

					850000000

					100000000

					19200000

					825000000

					19200000

					660000000>;

			};



			qcom,npu-pwrlevel@4 {

				reg = <4>;

				vreg = <6>;

				clk-freq = <19200000

					500000000

					1000000000

					1000000000

					533000000

					75000000

					806000000

					300000000

					19200000

					100000000

					200000000

					300000000

					300000000

					300000000

					19200000

					300000000

					19200000

					100000000

					1000000000

					100000000

					19200000

					1000000000

					19200000

					800000000>;

			};

		};

	};

};

qcom/lito.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -3583,6 +3583,7 @@ 
#include "lito-bus.dtsi"

#include "lito-gpu.dtsi"

#include "lito-thermal.dtsi"

#include "lito-npu.dtsi"



&ufs_phy_gdsc {

	status = "ok";