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Commit 67febff5 authored by Tony Truong's avatar Tony Truong
Browse files

dt-bindings: pcie: add L1.2 LTR scale and value 

Add L1.2 latency tolerance reporting (LTR) scale and value
option for devicetree.

Change-Id: I6f5c5ce60cd66ae8aad44c0c463c9898ac129450
parent 3e9c170e

bindings/pci/pci-msm.txt

+17 −0
Original line number Diff line number Diff line
@@ -260,6 +260,23 @@ Main node 
	Definition: The AUX clock is not synchronous to the Core clock to

		support L1ss



- qcom,l1-2-th-scale:

	Usage: optional

	Value type: <u32>

	Definition: Determines the multiplier for L1.2 LTR threshold value

		- 0	1ns

		- 1	32ns

		- 2	1us

		- 3	32us

		- 4	1ms

		- 5	32ms



- qcom,l1-2-th-value:

	Usage: optional

	Value type: <u32>

	Definition: L1.2 LTR threshold value to be multipled with scale to

		define L1.2 latency tolerance reporting (LTR)



- qcom,slv-addr-space-size:

	Usage: required

	Value type: <u32>