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Commit 63801f21 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
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drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent 



I stumbled on to some unimplemented errata. To be honest, I am not
really sure of the impact, just that the docs say to do.

No w/a name for this one.

v2: v1 was a stale thing which should have never seen the light of day.
(Haihao)

Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a3564d2b

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -4167,6 +4167,10 @@ 
#define GEN7_L3SQCREG4				0xb034

#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)



/* GEN8 chicken */

#define HDC_CHICKEN0				0x7300

#define  HDC_FORCE_NON_COHERENT			(1<<4)



/* WaCatErrorRejectionIssue */

#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030

#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)

drivers/gpu/drm/i915/intel_pm.c

+8 −0
Original line number Diff line number Diff line
@@ -5269,6 +5269,14 @@ static void gen8_init_clock_gating(struct drm_device *dev) 
			   I915_READ(CHICKEN_PIPESL_1(i) |

				     DPRS_MASK_VBLANK_SRD));

	}



	/* Use Force Non-Coherent whenever executing a 3D context. This is a

	 * workaround for for a possible hang in the unlikely event a TLB

	 * invalidation occurs during a PSD flush.

	 */

	I915_WRITE(HDC_CHICKEN0,

		   I915_READ(HDC_CHICKEN0) |

		   _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));

}



static void haswell_init_clock_gating(struct drm_device *dev)