clk: Move VDD voltage voting from core clock to top clock

Current vdd voting happens from top to core (clock on which the rate has
been requested), which has issues with sources which are slewing.
In the cases where the PLLs are slewing the RCGs should have the voltage
already maintained for the new frequency before the PLLs are slewed.
Modify clk_core_set_rate_nolock() so that it votes for all new frequency
voltages for the core clock and each of its parent clocks before physically
changing any rates.

Change-Id: Idf02bedcfb05a37e0c944ebe36d2dcf9032ae0d8
Signed-off-by: Taniya Das <tdas@codeaurora.org>