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Commit 618ef005 authored by Oscar Mateo's avatar Oscar Mateo Committed by Joonas Lahtinen
Browse files

drm/i915/guc: Move guc_interrupts_release next to guc_interrupts_capture 



They go better together.

Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
parent 35815ea9

drivers/gpu/drm/i915/i915_guc_submission.c

+24 −24
Original line number Diff line number Diff line
@@ -1189,6 +1189,30 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv) 
	dev_priv->rps.pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;

}



static void guc_interrupts_release(struct drm_i915_private *dev_priv)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	int irqs;



	/*

	 * tell all command streamers NOT to forward interrupts or vblank

	 * to GuC.

	 */

	irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);

	irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);

	for_each_engine(engine, dev_priv, id)

		I915_WRITE(RING_MODE_GEN7(engine), irqs);



	/* route all GT interrupts to the host */

	I915_WRITE(GUC_BCS_RCS_IER, 0);

	I915_WRITE(GUC_VCS2_VCS1_IER, 0);

	I915_WRITE(GUC_WD_VECS_IER, 0);



	dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;

	dev_priv->rps.pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;

}



int i915_guc_submission_enable(struct drm_i915_private *dev_priv)

{

	struct intel_guc *guc = &dev_priv->guc;
@@ -1252,30 +1276,6 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv) 
	return err;

}



static void guc_interrupts_release(struct drm_i915_private *dev_priv)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	int irqs;



	/*

	 * tell all command streamers NOT to forward interrupts or vblank

	 * to GuC.

	 */

	irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);

	irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);

	for_each_engine(engine, dev_priv, id)

		I915_WRITE(RING_MODE_GEN7(engine), irqs);



	/* route all GT interrupts to the host */

	I915_WRITE(GUC_BCS_RCS_IER, 0);

	I915_WRITE(GUC_VCS2_VCS1_IER, 0);

	I915_WRITE(GUC_WD_VECS_IER, 0);



	dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;

	dev_priv->rps.pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;

}



void i915_guc_submission_disable(struct drm_i915_private *dev_priv)

{

	struct intel_guc *guc = &dev_priv->guc;