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Commit 35815ea9 authored by Oscar Mateo's avatar Oscar Mateo Committed by Joonas Lahtinen
Browse files

drm/i915/guc: Split out the mmio_white_list struct 



We are going to need it for future platforms.

Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
parent b09935a6

drivers/gpu/drm/i915/i915_guc_submission.c

+2 −2
Original line number Diff line number Diff line
@@ -1049,11 +1049,11 @@ static int guc_ads_create(struct intel_guc *guc) 


	/* MMIO reg state */

	for_each_engine(engine, dev_priv, id) {

		blob->reg_state.mmio_white_list[engine->guc_id].mmio_start =

		blob->reg_state.white_list[engine->guc_id].mmio_start =

			engine->mmio_base + GUC_MMIO_WHITE_LIST_START;



		/* Nothing to be saved or restored for now. */

		blob->reg_state.mmio_white_list[engine->guc_id].count = 0;

		blob->reg_state.white_list[engine->guc_id].count = 0;

	}



	/*

drivers/gpu/drm/i915/intel_guc_fwif.h

+8 −7
Original line number Diff line number Diff line
@@ -409,16 +409,17 @@ struct guc_mmio_regset { 
	u32 number_of_registers;

} __packed;



struct guc_mmio_reg_state {

	struct guc_mmio_regset global_reg;

	struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];



/* MMIO registers that are set as non privileged */

	struct __packed {

struct mmio_white_list {

	u32 mmio_start;

	u32 offsets[GUC_MMIO_WHITE_LIST_MAX];

	u32 count;

	} mmio_white_list[GUC_MAX_ENGINES_NUM];

} __packed;



struct guc_mmio_reg_state {

	struct guc_mmio_regset global_reg;

	struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];

	struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM];

} __packed;



/* GuC Additional Data Struct */