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Commit 605cd25b authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: add dev_priv->pm_irq_mask 



Just like irq_mask and gt_irq_mask, use it to track the status of
GEN6_PMIMR so we don't need to read it again every time we call
snb_update_pm_irq.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f52ecbcf

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -1123,6 +1123,7 @@ typedef struct drm_i915_private { 
	/** Cached value of IMR to avoid reads in updating the bitfield */

	u32 irq_mask;

	u32 gt_irq_mask;

	u32 pm_irq_mask;



	struct work_struct hotplug_work;

	bool enable_hotplug_processing;

drivers/gpu/drm/i915/i915_irq.c

+7 −5
Original line number Diff line number Diff line
@@ -142,16 +142,17 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv, 
			      uint32_t interrupt_mask,

			      uint32_t enabled_irq_mask)

{

	uint32_t pmimr, new_val;

	uint32_t new_val;



	assert_spin_locked(&dev_priv->irq_lock);



	pmimr = new_val = I915_READ(GEN6_PMIMR);

	new_val = dev_priv->pm_irq_mask;

	new_val &= ~interrupt_mask;

	new_val |= (~enabled_irq_mask & interrupt_mask);



	if (new_val != pmimr) {

		I915_WRITE(GEN6_PMIMR, new_val);

	if (new_val != dev_priv->pm_irq_mask) {

		dev_priv->pm_irq_mask = new_val;

		I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);

		POSTING_READ(GEN6_PMIMR);

	}

}
@@ -2217,8 +2218,9 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) 
		if (HAS_VEBOX(dev))

			pm_irqs |= PM_VEBOX_USER_INTERRUPT;



		dev_priv->pm_irq_mask = 0xffffffff;

		I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));

		I915_WRITE(GEN6_PMIMR, 0xffffffff);

		I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);

		I915_WRITE(GEN6_PMIER, pm_irqs);

		POSTING_READ(GEN6_PMIER);

	}