msm: kgsl: Avoid register write miss for a fenced register

In adreno_gmu_fenced_write(), it is possible that the register write
is posted after reading the fence status register, which in this case
will return a Success. But the register write may be dropped. We can
avoid this by forcing the order of the read/write operations with a
barrier. Put a memory barrier after the register write to make sure
the write is posted before the register is read.

Change-Id: I7882c3e9d1f7e5182fedafe0b28727f777c7bd7f
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>