Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5e892cc6 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Move gpu_idle_level_names



gmu_idle_level_names is only used in one place in one file. It can be
removed from the header file and replaced with a simple static function.

Change-Id: Ic0dedbad45c4f177979d4f8bcef7a7f2b60dd0a7
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 16279b1e
Loading
Loading
Loading
Loading
+17 −1
Original line number Diff line number Diff line
@@ -842,6 +842,22 @@ static bool idle_trandition_complete(unsigned int idle_level,
	return true;
}

static const char *idle_level_name(int level)
{
	if (level == GPU_HW_ACTIVE)
		return "GPU_HW_ACTIVE";
	else if (level == GPU_HW_SPTP_PC)
		return "GPU_HW_SPTP_PC";
	else if (level == GPU_HW_IFPC)
		return "GPU_HW_IFPC";
	else if (level == GPU_HW_NAP)
		return "GPU_HW_NAP";
	else if (level == GPU_HW_MIN_VOLT)
		return "GPU_HW_MIN_VOLT";

	return "";
}

static int a6xx_gmu_wait_for_lowest_idle(struct kgsl_device *device)
{
	struct gmu_device *gmu = KGSL_GMU_DEVICE(device);
@@ -888,7 +904,7 @@ static int a6xx_gmu_wait_for_lowest_idle(struct kgsl_device *device)
		"----------------------[ GMU error ]----------------------\n");
	dev_err(&gmu->pdev->dev,
		"Timeout waiting for lowest idle level %s\n",
		gpu_idle_level_names[gmu->idle_level]);
		idle_level_name(gmu->idle_level));
	dev_err(&gmu->pdev->dev, "Start: %llx (absolute ticks)\n", ts1);
	dev_err(&gmu->pdev->dev, "Poll: %llx (ticks relative to start)\n",
		ts2-ts1);
+0 −10
Original line number Diff line number Diff line
@@ -87,16 +87,6 @@ enum gpu_idle_level {
	GPU_HW_SLUMBER = 0xF
};

static const char * const gpu_idle_level_names[] = {
	[GPU_HW_ACTIVE] = "GPU_HW_ACTIVE",
	[GPU_HW_SPTP_PC] = "GPU_HW_SPTP_PC",
	[GPU_HW_IFPC] = "GPU_HW_IFPC",
	[GPU_HW_NAP] = "GPU_HW_NAP",
	[GPU_HW_MIN_VOLT] = "GPU_HW_MIN_VOLT",
	[GPU_HW_MIN_DDR] = "GPU_HW_MIN_DDR",
	[GPU_HW_SLUMBER] = "GPU_HW_SLUMBER"
};

/*
 * Wait time before trying to write the register again.
 * Hopefully the GMU has finished waking up during this delay.