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Commit 16279b1e authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Remove unneeded GMU core checks 



If the device has a valid gmu_dev_ops struct defined then we know that
the GMU/RGMU is enabled and we don't need an additional check in the
functions.

Change-Id: Ic0dedbadfa50015459ca254c18a443e2bc2b565b
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 0b10adba

drivers/gpu/msm/adreno_a6xx_gmu.c

+2 −25
Original line number Diff line number Diff line
@@ -556,9 +556,6 @@ static int a6xx_gmu_oob_set(struct kgsl_device *device, 
	int ret = 0;

	int set, check;



	if (!gmu_core_isenabled(device))

		return 0;



	if (!adreno_is_a630(adreno_dev) && !adreno_is_a615_family(adreno_dev)) {

		set = BIT(30 - req * 2);

		check = BIT(31 - req);
@@ -603,9 +600,6 @@ static inline void a6xx_gmu_oob_clear(struct kgsl_device *device, 
	struct gmu_device *gmu = KGSL_GMU_DEVICE(device);

	int clear;



	if (!gmu_core_isenabled(device))

		return;



	if (!adreno_is_a630(adreno_dev) && !adreno_is_a615_family(adreno_dev)) {

		clear = BIT(31 - req * 2);

		if (req >= 6) {
@@ -694,9 +688,6 @@ static int a6xx_complete_rpmh_votes(struct kgsl_device *device) 
{

	int ret = 0;



	if (!gmu_core_isenabled(device))

		return ret;



	ret |= timed_poll_check_rscc(device, A6XX_RSCC_TCS0_DRV0_STATUS,

			BIT(0), GPU_RESET_TIMEOUT, BIT(0));

	ret |= timed_poll_check_rscc(device, A6XX_RSCC_TCS1_DRV0_STATUS,
@@ -858,9 +849,6 @@ static int a6xx_gmu_wait_for_lowest_idle(struct kgsl_device *device) 
	unsigned long t;

	uint64_t ts1, ts2, ts3;



	if (!gmu_core_isenabled(device))

		return 0;



	ts1 = read_AO_counter(device);



	t = jiffies + msecs_to_jiffies(GMU_IDLE_TIMEOUT);
@@ -1070,10 +1058,6 @@ static int a6xx_gmu_load_firmware(struct kgsl_device *device) 
	struct gmu_block_header *blk;

	int ret, offset = 0;



	/* there is no GMU */

	if (!gmu_core_isenabled(device))

		return 0;



	/* GMU fw already saved and verified so do nothing new */

	if (gmu->fw_image)

		return 0;
@@ -1448,8 +1432,7 @@ static int a6xx_gmu_ifpc_store(struct kgsl_device *device, 
	struct gmu_device *gmu = KGSL_GMU_DEVICE(device);

	unsigned int requested_idle_level;



	if (!gmu_core_isenabled(device) ||

			!ADRENO_FEATURE(adreno_dev, ADRENO_IFPC))

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_IFPC))

		return -EINVAL;



	if ((val && gmu->idle_level >= GPU_HW_IFPC) ||
@@ -1481,7 +1464,7 @@ static unsigned int a6xx_gmu_ifpc_show(struct kgsl_device *device) 
{

	struct gmu_device *gmu = KGSL_GMU_DEVICE(device);



	return gmu_core_isenabled(device) && gmu->idle_level  >= GPU_HW_IFPC;

	return gmu->idle_level >= GPU_HW_IFPC;

}



struct gmu_mem_type_desc {
@@ -1670,9 +1653,6 @@ static void a6xx_gmu_snapshot(struct kgsl_device *device, 
{

	unsigned int val;



	if (!gmu_core_isenabled(device))

		return;



	a6xx_gmu_snapshot_versions(device, snapshot);



	a6xx_gmu_snapshot_memories(device, snapshot);
@@ -1705,9 +1685,6 @@ static int a6xx_gmu_wait_for_active_transition( 
	unsigned int reg, num_retries;

	struct gmu_device *gmu = KGSL_GMU_DEVICE(device);



	if (!gmu_core_isenabled(device))

		return 0;



	gmu_core_regread(device,

		A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE, &reg);

drivers/gpu/msm/adreno_a6xx_rgmu.c

+3 −17
Original line number Diff line number Diff line
@@ -99,9 +99,6 @@ static int a6xx_rgmu_oob_set(struct kgsl_device *device, 
	struct rgmu_device *rgmu = KGSL_RGMU_DEVICE(device);

	int ret, set, check;



	if (!gmu_core_isenabled(device))

		return 0;



	set = BIT(req + 16);

	check = BIT(req + 16);
@@ -136,9 +133,6 @@ static int a6xx_rgmu_oob_set(struct kgsl_device *device, 
static inline void a6xx_rgmu_oob_clear(struct kgsl_device *device,

		enum oob_request req)

{

	if (!gmu_core_isenabled(device))

		return;



	gmu_core_regwrite(device, A6XX_GMU_HOST2GMU_INTR_SET, BIT(req + 24));

	trace_kgsl_gmu_oob_clear(BIT(req + 24));

}
@@ -201,8 +195,7 @@ static int a6xx_rgmu_ifpc_store(struct kgsl_device *device, 
	struct rgmu_device *rgmu = KGSL_RGMU_DEVICE(device);

	unsigned int requested_idle_level;



	if (!gmu_core_isenabled(device) ||

		!ADRENO_FEATURE(adreno_dev, ADRENO_IFPC))

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_IFPC))

		return -EINVAL;



	if (val)
@@ -229,7 +222,7 @@ static unsigned int a6xx_rgmu_ifpc_show(struct kgsl_device *device) 
{

	struct rgmu_device *rgmu = KGSL_RGMU_DEVICE(device);



	return gmu_core_isenabled(device) && rgmu->idle_level == GPU_HW_IFPC;

	return rgmu->idle_level == GPU_HW_IFPC;

}
@@ -263,8 +256,7 @@ static int a6xx_rgmu_wait_for_lowest_idle(struct kgsl_device *device) 
	unsigned long t;

	uint64_t ts1, ts2, ts3;



	if (!gmu_core_isenabled(device) ||

			rgmu->idle_level != GPU_HW_IFPC)

	if (rgmu->idle_level != GPU_HW_IFPC)

		return 0;



	ts1 = read_AO_counter(device);
@@ -462,9 +454,6 @@ static int a6xx_rgmu_gpu_pwrctrl(struct kgsl_device *device, 
{

	int ret = 0;



	if (!gmu_core_isenabled(device))

		return 0;



	switch (mode) {

	case GMU_FW_START:

		ret = a6xx_rgmu_fw_start(device, arg1);
@@ -502,9 +491,6 @@ static int a6xx_rgmu_load_firmware(struct kgsl_device *device) 
	const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev);

	int ret;



	if (!gmu_core_isenabled(device))

		return 0;



	/* RGMU fw already saved and verified so do nothing new */

	if (rgmu->fw_hostptr)

		return 0;