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Commit 5e0ad9f6 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/ecam' into next 

* pci/ecam:
  PCI: Explain ARM64 ACPI/MCFG quirk Kconfig and build strategy
  PCI: Add MCFG quirks for X-Gene host controller
  PCI: Add MCFG quirks for Cavium ThunderX pass1.x host controller
  PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller
  PCI: thunder-pem: Factor out resource lookup
  PCI: Add MCFG quirks for HiSilicon Hip05/06/07 host controllers
  PCI: Add MCFG quirks for Qualcomm QDF2432 host controller
  PCI/ACPI: Provide acpi_get_rc_resources() for ARM64 platform
  PCI/ACPI: Check for platform-specific MCFG quirks
  PCI/ACPI: Extend pci_mcfg_lookup() to return ECAM config accessors
  arm64: PCI: Exclude ACPI "consumer" resources from host bridge windows
  arm64: PCI: Manage controller-specific data on per-controller basis
  arm64: PCI: Search ACPI namespace to ensure ECAM space is reserved
  arm64: PCI: Add local struct device pointers
  ACPI: Add acpi_resource_consumer() to find device that claims a resource
parents a7d51491 ca5ab37b

arch/arm64/kernel/pci.c

+43 −24
Original line number Diff line number Diff line
@@ -114,6 +114,19 @@ int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 
	return 0;

}



static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)

{

	struct resource_entry *entry, *tmp;

	int status;



	status = acpi_pci_probe_root_resources(ci);

	resource_list_for_each_entry_safe(entry, tmp, &ci->resources) {

		if (!(entry->res->flags & IORESOURCE_WINDOW))

			resource_list_destroy_entry(entry);

	}

	return status;

}



/*

 * Lookup the bus range for the domain in MCFG, and set up config space

 * mapping.
@@ -121,31 +134,33 @@ int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 
static struct pci_config_window *

pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root)

{

	struct device *dev = &root->device->dev;

	struct resource *bus_res = &root->secondary;

	u16 seg = root->segment;

	struct pci_config_window *cfg;

	struct pci_ecam_ops *ecam_ops;

	struct resource cfgres;

	unsigned int bsz;



	/* Use address from _CBA if present, otherwise lookup MCFG */

	if (!root->mcfg_addr)

		root->mcfg_addr = pci_mcfg_lookup(seg, bus_res);

	struct acpi_device *adev;

	struct pci_config_window *cfg;

	int ret;



	if (!root->mcfg_addr) {

		dev_err(&root->device->dev, "%04x:%pR ECAM region not found\n",

			seg, bus_res);

	ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops);

	if (ret) {

		dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res);

		return NULL;

	}



	bsz = 1 << pci_generic_ecam_ops.bus_shift;

	cfgres.start = root->mcfg_addr + bus_res->start * bsz;

	cfgres.end = cfgres.start + resource_size(bus_res) * bsz - 1;

	cfgres.flags = IORESOURCE_MEM;

	cfg = pci_ecam_create(&root->device->dev, &cfgres, bus_res,

			      &pci_generic_ecam_ops);

	adev = acpi_resource_consumer(&cfgres);

	if (adev)

		dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres,

			 dev_name(&adev->dev));

	else

		dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n",

			 &cfgres);



	cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops);

	if (IS_ERR(cfg)) {

		dev_err(&root->device->dev, "%04x:%pR error %ld mapping ECAM\n",

			seg, bus_res, PTR_ERR(cfg));

		dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res,

			PTR_ERR(cfg));

		return NULL;

	}
@@ -159,33 +174,37 @@ static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) 


	ri = container_of(ci, struct acpi_pci_generic_root_info, common);

	pci_ecam_free(ri->cfg);

	kfree(ci->ops);

	kfree(ri);

}



static struct acpi_pci_root_ops acpi_pci_root_ops = {

	.release_info = pci_acpi_generic_release_info,

};



/* Interface called from ACPI code to setup PCI host controller */

struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)

{

	int node = acpi_get_node(root->device->handle);

	struct acpi_pci_generic_root_info *ri;

	struct pci_bus *bus, *child;

	struct acpi_pci_root_ops *root_ops;



	ri = kzalloc_node(sizeof(*ri), GFP_KERNEL, node);

	if (!ri)

		return NULL;



	root_ops = kzalloc_node(sizeof(*root_ops), GFP_KERNEL, node);

	if (!root_ops)

		return NULL;



	ri->cfg = pci_acpi_setup_ecam_mapping(root);

	if (!ri->cfg) {

		kfree(ri);

		kfree(root_ops);

		return NULL;

	}



	acpi_pci_root_ops.pci_ops = &ri->cfg->ops->pci_ops;

	bus = acpi_pci_root_create(root, &acpi_pci_root_ops, &ri->common,

				   ri->cfg);

	root_ops->release_info = pci_acpi_generic_release_info;

	root_ops->prepare_resources = pci_acpi_root_prepare_resources;

	root_ops->pci_ops = &ri->cfg->ops->pci_ops;

	bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg);

	if (!bus)

		return NULL;

drivers/acpi/pci_mcfg.c

+187 −3
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include <linux/kernel.h>

#include <linux/pci.h>

#include <linux/pci-acpi.h>

#include <linux/pci-ecam.h>



/* Structure to hold entries from the MCFG table */

struct mcfg_entry {
@@ -32,12 +33,166 @@ struct mcfg_entry { 
	u8			bus_end;

};



#ifdef CONFIG_PCI_QUIRKS

struct mcfg_fixup {

	char oem_id[ACPI_OEM_ID_SIZE + 1];

	char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];

	u32 oem_revision;

	u16 segment;

	struct resource bus_range;

	struct pci_ecam_ops *ops;

	struct resource cfgres;

};



#define MCFG_BUS_RANGE(start, end)	DEFINE_RES_NAMED((start),	\

						((end) - (start) + 1),	\

						NULL, IORESOURCE_BUS)

#define MCFG_BUS_ANY			MCFG_BUS_RANGE(0x0, 0xff)



static struct mcfg_fixup mcfg_quirks[] = {

/*	{ OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */



#define QCOM_ECAM32(seg) \

	{ "QCOM  ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }

	QCOM_ECAM32(0),

	QCOM_ECAM32(1),

	QCOM_ECAM32(2),

	QCOM_ECAM32(3),

	QCOM_ECAM32(4),

	QCOM_ECAM32(5),

	QCOM_ECAM32(6),

	QCOM_ECAM32(7),



#define HISI_QUAD_DOM(table_id, seg, ops) \

	{ "HISI  ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \

	{ "HISI  ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \

	{ "HISI  ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \

	{ "HISI  ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }

	HISI_QUAD_DOM("HIP05   ",  0, &hisi_pcie_ops),

	HISI_QUAD_DOM("HIP06   ",  0, &hisi_pcie_ops),

	HISI_QUAD_DOM("HIP07   ",  0, &hisi_pcie_ops),

	HISI_QUAD_DOM("HIP07   ",  4, &hisi_pcie_ops),

	HISI_QUAD_DOM("HIP07   ",  8, &hisi_pcie_ops),

	HISI_QUAD_DOM("HIP07   ", 12, &hisi_pcie_ops),



#define THUNDER_PEM_RES(addr, node) \

	DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)

#define THUNDER_PEM_QUIRK(rev, node) \

	{ "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY,	    \

	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) },  \

	{ "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY,	    \

	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) },  \

	{ "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY,	    \

	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) },  \

	{ "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY,	    \

	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) },  \

	{ "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY,	    \

	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) },  \

	{ "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY,	    \

	  &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }

	/* SoC pass2.x */

	THUNDER_PEM_QUIRK(1, 0),

	THUNDER_PEM_QUIRK(1, 1),



#define THUNDER_ECAM_QUIRK(rev, seg)					\

	{ "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY,			\

	&pci_thunder_ecam_ops }

	/* SoC pass1.x */

	THUNDER_PEM_QUIRK(2, 0),	/* off-chip devices */

	THUNDER_PEM_QUIRK(2, 1),	/* off-chip devices */

	THUNDER_ECAM_QUIRK(2,  0),

	THUNDER_ECAM_QUIRK(2,  1),

	THUNDER_ECAM_QUIRK(2,  2),

	THUNDER_ECAM_QUIRK(2,  3),

	THUNDER_ECAM_QUIRK(2, 10),

	THUNDER_ECAM_QUIRK(2, 11),

	THUNDER_ECAM_QUIRK(2, 12),

	THUNDER_ECAM_QUIRK(2, 13),



#define XGENE_V1_ECAM_MCFG(rev, seg) \

	{"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \

		&xgene_v1_pcie_ecam_ops }

#define XGENE_V2_ECAM_MCFG(rev, seg) \

	{"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \

		&xgene_v2_pcie_ecam_ops }

	/* X-Gene SoC with v1 PCIe controller */

	XGENE_V1_ECAM_MCFG(1, 0),

	XGENE_V1_ECAM_MCFG(1, 1),

	XGENE_V1_ECAM_MCFG(1, 2),

	XGENE_V1_ECAM_MCFG(1, 3),

	XGENE_V1_ECAM_MCFG(1, 4),

	XGENE_V1_ECAM_MCFG(2, 0),

	XGENE_V1_ECAM_MCFG(2, 1),

	XGENE_V1_ECAM_MCFG(2, 2),

	XGENE_V1_ECAM_MCFG(2, 3),

	XGENE_V1_ECAM_MCFG(2, 4),

	/* X-Gene SoC with v2.1 PCIe controller */

	XGENE_V2_ECAM_MCFG(3, 0),

	XGENE_V2_ECAM_MCFG(3, 1),

	/* X-Gene SoC with v2.2 PCIe controller */

	XGENE_V2_ECAM_MCFG(4, 0),

	XGENE_V2_ECAM_MCFG(4, 1),

	XGENE_V2_ECAM_MCFG(4, 2),

};



static char mcfg_oem_id[ACPI_OEM_ID_SIZE];

static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];

static u32 mcfg_oem_revision;



static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,

				  struct resource *bus_range)

{

	if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&

	    !memcmp(f->oem_table_id, mcfg_oem_table_id,

	            ACPI_OEM_TABLE_ID_SIZE) &&

	    f->oem_revision == mcfg_oem_revision &&

	    f->segment == segment &&

	    resource_contains(&f->bus_range, bus_range))

		return 1;



	return 0;

}

#endif



static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,

				  struct resource *cfgres,

				  struct pci_ecam_ops **ecam_ops)

{

#ifdef CONFIG_PCI_QUIRKS

	u16 segment = root->segment;

	struct resource *bus_range = &root->secondary;

	struct mcfg_fixup *f;

	int i;



	for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {

		if (pci_mcfg_quirk_matches(f, segment, bus_range)) {

			if (f->cfgres.start)

				*cfgres = f->cfgres;

			if (f->ops)

				*ecam_ops =  f->ops;

			dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",

				 cfgres, bus_range, *ecam_ops);

			return;

		}

	}

#endif

}



/* List to save MCFG entries */

static LIST_HEAD(pci_mcfg_list);



phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res)

int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,

		    struct pci_ecam_ops **ecam_ops)

{

	struct pci_ecam_ops *ops = &pci_generic_ecam_ops;

	struct resource *bus_res = &root->secondary;

	u16 seg = root->segment;

	struct mcfg_entry *e;

	struct resource res;



	/* Use address from _CBA if present, otherwise lookup MCFG */

	if (root->mcfg_addr)

		goto skip_lookup;



	/*

	 * We expect exact match, unless MCFG entry end bus covers more than
@@ -45,10 +200,32 @@ phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res) 
	 */

	list_for_each_entry(e, &pci_mcfg_list, list) {

		if (e->segment == seg && e->bus_start == bus_res->start &&

		    e->bus_end >= bus_res->end)

			return e->addr;

		    e->bus_end >= bus_res->end) {

			root->mcfg_addr = e->addr;

		}



	}



skip_lookup:

	memset(&res, 0, sizeof(res));

	if (root->mcfg_addr) {

		res.start = root->mcfg_addr + (bus_res->start << 20);

		res.end = res.start + (resource_size(bus_res) << 20) - 1;

		res.flags = IORESOURCE_MEM;

	}



	/*

	 * Allow quirks to override default ECAM ops and CFG resource

	 * range.  This may even fabricate a CFG resource range in case

	 * MCFG does not have it.  Invalid CFG start address means MCFG

	 * firmware bug or we need another quirk in array.

	 */

	pci_mcfg_apply_quirks(root, &res, &ops);

	if (!res.start)

		return -ENXIO;



	*cfgres = res;

	*ecam_ops = ops;

	return 0;

}
@@ -79,6 +256,13 @@ static __init int pci_mcfg_parse(struct acpi_table_header *header) 
		list_add(&e->list, &pci_mcfg_list);

	}



#ifdef CONFIG_PCI_QUIRKS

	/* Save MCFG IDs and revision for quirks matching */

	memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);

	memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);

	mcfg_oem_revision = header->oem_revision;

#endif



	pr_info("MCFG table detected, %d entries\n", n);

	return 0;

}

drivers/acpi/resource.c

+57 −0
Original line number Diff line number Diff line
@@ -664,3 +664,60 @@ int acpi_dev_filter_resource_type(struct acpi_resource *ares, 
	return (type & types) ? 0 : 1;

}

EXPORT_SYMBOL_GPL(acpi_dev_filter_resource_type);



static int acpi_dev_consumes_res(struct acpi_device *adev, struct resource *res)

{

	struct list_head resource_list;

	struct resource_entry *rentry;

	int ret, found = 0;



	INIT_LIST_HEAD(&resource_list);

	ret = acpi_dev_get_resources(adev, &resource_list, NULL, NULL);

	if (ret < 0)

		return 0;



	list_for_each_entry(rentry, &resource_list, node) {

		if (resource_contains(rentry->res, res)) {

			found = 1;

			break;

		}



	}



	acpi_dev_free_resource_list(&resource_list);

	return found;

}



static acpi_status acpi_res_consumer_cb(acpi_handle handle, u32 depth,

					 void *context, void **ret)

{

	struct resource *res = context;

	struct acpi_device **consumer = (struct acpi_device **) ret;

	struct acpi_device *adev;



	if (acpi_bus_get_device(handle, &adev))

		return AE_OK;



	if (acpi_dev_consumes_res(adev, res)) {

		*consumer = adev;

		return AE_CTRL_TERMINATE;

	}



	return AE_OK;

}



/**

 * acpi_resource_consumer - Find the ACPI device that consumes @res.

 * @res: Resource to search for.

 *

 * Search the current resource settings (_CRS) of every ACPI device node

 * for @res.  If we find an ACPI device whose _CRS includes @res, return

 * it.  Otherwise, return NULL.

 */

struct acpi_device *acpi_resource_consumer(struct resource *res)

{

	struct acpi_device *consumer = NULL;



	acpi_get_devices(NULL, acpi_res_consumer_cb, res, (void **) &consumer);

	return consumer;

}

drivers/pci/ecam.c

+12 −0
Original line number Diff line number Diff line
@@ -162,3 +162,15 @@ struct pci_ecam_ops pci_generic_ecam_ops = { 
		.write		= pci_generic_config_write,

	}

};



#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)

/* ECAM ops for 32-bit access only (non-compliant) */

struct pci_ecam_ops pci_32b_ops = {

	.bus_shift	= 20,

	.pci_ops	= {

		.map_bus	= pci_ecam_map_bus,

		.read		= pci_generic_config_read32,

		.write		= pci_generic_config_write32,

	}

};

#endif

drivers/pci/host/Kconfig

+6 −4
Original line number Diff line number Diff line
@@ -133,8 +133,8 @@ config PCIE_XILINX 


config PCI_XGENE

	bool "X-Gene PCIe controller"

	depends on ARCH_XGENE

	depends on OF

	depends on ARM64

	depends on OF || (ACPI && PCI_QUIRKS)

	select PCIEPORTBUS

	help

	  Say Y here if you want internal PCI support on APM X-Gene SoC.
@@ -240,14 +240,16 @@ config PCIE_QCOM 


config PCI_HOST_THUNDER_PEM

	bool "Cavium Thunder PCIe controller to off-chip devices"

	depends on OF && ARM64

	depends on ARM64

	depends on OF || (ACPI && PCI_QUIRKS)

	select PCI_HOST_COMMON

	help

	  Say Y here if you want PCIe support for CN88XX Cavium Thunder SoCs.



config PCI_HOST_THUNDER_ECAM

	bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"

	depends on OF && ARM64

	depends on ARM64

	depends on OF || (ACPI && PCI_QUIRKS)

	select PCI_HOST_COMMON

	help

	  Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.