Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5dd696ae authored by Trigger Huang's avatar Trigger Huang Committed by Alex Deucher
Browse files

drm/amdgpu: Bypass GMC/UVD/VCE hw_fini in SR-IOV



On vega10, some hw finish operations should not be applied in SR-IOV
case. This works as workaround to fix multi-VFs reboot/shutdown
issues.

Signed-off-by: default avatarTrigger Huang <trigger.huang@amd.com>
Reviewed-by: default avatarXiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: default avatarMonk Liu <monk.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2cb681b6
Loading
Loading
Loading
Loading
+6 −0
Original line number Diff line number Diff line
@@ -781,6 +781,12 @@ static int gmc_v9_0_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (amdgpu_sriov_vf(adev)) {
		/* full access mode, so don't touch any GMC register */
		DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
		return 0;
	}

	amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
	gmc_v9_0_gart_disable(adev);

+7 −1
Original line number Diff line number Diff line
@@ -562,7 +562,13 @@ static int uvd_v7_0_hw_fini(void *handle)
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	struct amdgpu_ring *ring = &adev->uvd.ring;

	if (!amdgpu_sriov_vf(adev))
		uvd_v7_0_stop(adev);
	else {
		/* full access mode, so don't touch any UVD register */
		DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
	}

	ring->ready = false;

	return 0;
+8 −2
Original line number Diff line number Diff line
@@ -505,8 +505,14 @@ static int vce_v4_0_hw_fini(void *handle)
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	int i;

	if (!amdgpu_sriov_vf(adev)) {
		/* vce_v4_0_wait_for_idle(handle); */
		vce_v4_0_stop(adev);
	} else {
		/* full access mode, so don't touch any VCE register */
		DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
	}

	for (i = 0; i < adev->vce.num_rings; i++)
		adev->vce.ring[i].ready = false;