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Commit 589c603b authored by Tushar Behera's avatar Tushar Behera Committed by Mike Turquette
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clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clock 



'mout_mpll' is added the list of parent clocks for 'mout_cpu'.
'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll'
should be added to the list of parent clocks.

This results in an error when cpufreq driver for EXYNOS5250 tries to
set 'mout_mpll' as a parent for 'mout_cpu'.

clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu

Signed-off-by: default avatarTushar Behera <tushar.behera@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 39b72d89

drivers/clk/samsung/clk-exynos5250.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -155,7 +155,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = { 




/* list of all parent clock list */

/* list of all parent clock list */

PNAME(mout_apll_p)	= { "fin_pll", "fout_apll", };

PNAME(mout_apll_p)	= { "fin_pll", "fout_apll", };

PNAME(mout_cpu_p)	= { "mout_apll", "mout_mpll", };

PNAME(mout_cpu_p)	= { "mout_apll", "sclk_mpll", };

PNAME(mout_mpll_fout_p)	= { "fout_mplldiv2", "fout_mpll" };

PNAME(mout_mpll_fout_p)	= { "fout_mplldiv2", "fout_mpll" };

PNAME(mout_mpll_p)	= { "fin_pll", "mout_mpll_fout" };

PNAME(mout_mpll_p)	= { "fin_pll", "mout_mpll_fout" };

PNAME(mout_bpll_fout_p)	= { "fout_bplldiv2", "fout_bpll" };

PNAME(mout_bpll_fout_p)	= { "fout_bplldiv2", "fout_bpll" };