Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 39b72d89 authored by Tushar Behera's avatar Tushar Behera Committed by Mike Turquette
Browse files

clk: exynos5250: Update cpufreq related clocks for EXYNOS5250 



cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot
currently pass the clock names through a device tree node. Instead, we
need to make them available through a global alias.

cpufreq driver for EXYNOS5250 requires four clocks - 'armclk',
'mout_cpu', 'mout_mpll' and 'mout_apll'.

'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll'
and 'mout_apll' are now defined with an alias.

Signed-off-by: default avatarTushar Behera <tushar.behera@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 72b5322f

drivers/clk/samsung/clk-exynos5250.c

+3 −3
Original line number Diff line number Diff line
@@ -208,10 +208,10 @@ struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { 
};



struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {

	MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),

	MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),

	MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"),

	MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),

	MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),

	MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1),

	MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),

	MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),

	MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),

	MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),