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Commit 57ea8c7b authored by Shaoyun Liu's avatar Shaoyun Liu Committed by Alex Deucher
Browse files

drm/amdgpu: NO KIQ usage on nbio hdp flush routine 



nbio hdp flush routine are called within atomic context.
Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register
since this register has its own VF copy

Signed-off-by: default avatarShaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c708535e

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

+1 −1
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) 


void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)

{

	WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);

	WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);

}



u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable) 


void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)

{

	WREG32_SOC15(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);

	WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);

}



u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)