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Commit 54f34562 authored by Amelie Delaunay's avatar Amelie Delaunay Committed by Greg Kroah-Hartman
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dmaengine: stm32-mdma: remove GISR1 register



[ Upstream commit 9d6a2d92e450926c483e45eaf426080a19219f4e ]

GISR1 was described in a not up-to-date documentation when the stm32-mdma
driver has been developed. This register has not been added in reference
manual of STM32 SoC with MDMA, which have only 32 MDMA channels.
So remove it from stm32-mdma driver.

Fixes: a4ffb13c ("dmaengine: Add STM32 MDMA driver")
Signed-off-by: default avatarAmelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20220504155322.121431-2-amelie.delaunay@foss.st.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 51eb1bb6
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+5 −16
Original line number Diff line number Diff line
@@ -50,7 +50,6 @@
					 STM32_MDMA_SHIFT(mask))

#define STM32_MDMA_GISR0		0x0000 /* MDMA Int Status Reg 1 */
#define STM32_MDMA_GISR1		0x0004 /* MDMA Int Status Reg 2 */

/* MDMA Channel x interrupt/status register */
#define STM32_MDMA_CISR(x)		(0x40 + 0x40 * (x)) /* x = 0..62 */
@@ -206,7 +205,7 @@

#define STM32_MDMA_MAX_BUF_LEN		128
#define STM32_MDMA_MAX_BLOCK_LEN	65536
#define STM32_MDMA_MAX_CHANNELS		63
#define STM32_MDMA_MAX_CHANNELS		32
#define STM32_MDMA_MAX_REQUESTS		256
#define STM32_MDMA_MAX_BURST		128
#define STM32_MDMA_VERY_HIGH_PRIORITY	0x11
@@ -1361,21 +1360,11 @@ static irqreturn_t stm32_mdma_irq_handler(int irq, void *devid)

	/* Find out which channel generates the interrupt */
	status = readl_relaxed(dmadev->base + STM32_MDMA_GISR0);
	if (status) {
		id = __ffs(status);
	} else {
		status = readl_relaxed(dmadev->base + STM32_MDMA_GISR1);
	if (!status) {
		dev_dbg(mdma2dev(dmadev), "spurious it\n");
		return IRQ_NONE;
	}
	id = __ffs(status);
		/*
		 * As GISR0 provides status for channel id from 0 to 31,
		 * so GISR1 provides status for channel id from 32 to 62
		 */
		id += 32;
	}

	chan = &dmadev->chan[id];
	if (!chan) {