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Commit 54e14ae2 authored by Ulrich Hecht's avatar Ulrich Hecht Committed by Greg Kroah-Hartman
Browse files

serial: sh-sci: add FIFO trigger bits 



Defines the bits controlling FIFO thresholds, adds the additional
HSCIF registers to the register map.

Signed-off-by: default avatarUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0832a462

drivers/tty/serial/sh-sci.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -373,6 +373,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 
			[HSSRR]		= { 0x40, 16 },

			[HSSRR]		= { 0x40, 16 },

			[SCDL]		= { 0x30, 16 },

			[SCDL]		= { 0x30, 16 },

			[SCCKS]		= { 0x34, 16 },

			[SCCKS]		= { 0x34, 16 },

			[HSRTRGR]	= { 0x54, 16 },

			[HSTTRGR]	= { 0x58, 16 },

		},

		},

		.fifosize = 128,

		.fifosize = 128,

		.overrun_reg = SCLSR,

		.overrun_reg = SCLSR,

drivers/tty/serial/sh-sci.h

+6 −0
Original line number Original line Diff line number Diff line
@@ -29,6 +29,8 @@ enum { 
	SCPDR,				/* Serial Port Data Register */

	SCPDR,				/* Serial Port Data Register */

	SCDL,				/* BRG Frequency Division Register */

	SCDL,				/* BRG Frequency Division Register */

	SCCKS,				/* BRG Clock Select Register */

	SCCKS,				/* BRG Clock Select Register */

	HSRTRGR,			/* Rx FIFO Data Count Trigger Register */

	HSTTRGR,			/* Tx FIFO Data Count Trigger Register */





	SCIx_NR_REGS,

	SCIx_NR_REGS,

};

};
@@ -99,6 +101,10 @@ enum { 
#define SCIF_BREAK_CLEAR	(u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))

#define SCIF_BREAK_CLEAR	(u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))





/* SCFCR (FIFO Control Register) */

/* SCFCR (FIFO Control Register) */

#define SCFCR_RTRG1	BIT(7)	/* Receive FIFO Data Count Trigger */

#define SCFCR_RTRG0	BIT(6)

#define SCFCR_TTRG1	BIT(5)	/* Transmit FIFO Data Count Trigger */

#define SCFCR_TTRG0	BIT(4)

#define SCFCR_MCE	BIT(3)	/* Modem Control Enable */

#define SCFCR_MCE	BIT(3)	/* Modem Control Enable */

#define SCFCR_TFRST	BIT(2)	/* Transmit FIFO Data Register Reset */

#define SCFCR_TFRST	BIT(2)	/* Transmit FIFO Data Register Reset */

#define SCFCR_RFRST	BIT(1)	/* Receive FIFO Data Register Reset */

#define SCFCR_RFRST	BIT(1)	/* Receive FIFO Data Register Reset */