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Commit 5438ad95 authored by Seungwon Jeon's avatar Seungwon Jeon Committed by Chris Ball
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mmc: omap: clarify DDR timing mode between SD-UHS and eMMC 



Replaced UHS_DDR50 with MMC_DDR52.

Signed-off-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Acked-by: default avatarBalaji T K <balajitk@ti.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarChris Ball <chris@printf.net>
parent 6dad6c95

drivers/mmc/host/omap_hsmmc.c

+2 −2
Original line number Diff line number Diff line
@@ -582,7 +582,7 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 
	 *	- MMC/SD clock coming out of controller > 25MHz

	 */

	if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&

	    (ios->timing != MMC_TIMING_UHS_DDR50) &&

	    (ios->timing != MMC_TIMING_MMC_DDR52) &&

	    ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {

		regval = OMAP_HSMMC_READ(host->base, HCTL);

		if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
@@ -602,7 +602,7 @@ static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 
	u32 con;



	con = OMAP_HSMMC_READ(host->base, CON);

	if (ios->timing == MMC_TIMING_UHS_DDR50)

	if (ios->timing == MMC_TIMING_MMC_DDR52)

		con |= DDR;	/* configure in DDR mode */

	else

		con &= ~DDR;