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Commit 536a2311 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add cpufreq-hw node for Bengal"

parents be8d8ba8 6e796c55

bindings/cpufreq/cpufreq-qcom-hw.txt

+5 −0
Original line number Diff line number Diff line
@@ -36,6 +36,11 @@ Properties: 
	Value type:	<u32>

	Definition:	Size of the LUT row size.



- qcom,lut-max-entries

	Usage:		Optional

	Value type:	<u32>

	Definition:	Size of the LUT entries.



- qcom,skip-enable-check

	Usage:		Optional

	Value type:	bool

qcom/bengal.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;

			L2_0: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <2>;
@@ -67,6 +68,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;



			L1_I_1: l1-icache {

				compatible = "arm,arch-cache";
@@ -87,6 +89,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;



			L1_I_2: l1-icache {

				compatible = "arm,arch-cache";
@@ -107,6 +110,7 @@ 
			d-cache-size = <0x8000>;

			i-cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 7>;



			L1_I_3: l1-icache {

				compatible = "arm,arch-cache";
@@ -127,6 +131,7 @@ 
			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;

			L2_1: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <2>;
@@ -151,6 +156,7 @@ 
			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;



			L1_I_101: l1-icache {

				compatible = "arm,arch-cache";
@@ -171,6 +177,7 @@ 
			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;



			L1_I_102: l1-icache {

				compatible = "arm,arch-cache";
@@ -191,6 +198,7 @@ 
			d-cache-size = <0x10000>;

			i-cache-size = <0x10000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 1 7>;



			L1_I_103: l1-icache {

				compatible = "arm,arch-cache";
@@ -1214,6 +1222,17 @@ 
		#clock-cells = <1>;

	};



	cpufreq_hw: qcom,cpufreq-hw {

		compatible = "qcom,cpufreq-hw";

		reg = <0xf521000 0x1000>, <0xf523000 0x1000>;

		reg-names = "freq-domain0", "freq-domain1";

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		qcom,no-accumulative-counter;

		qcom,max-lut-entries = <12>;

		#freq-domain-cells = <2>;

	};



	tcsr_mutex_block: syscon@00340000 {

		compatible = "syscon";

		reg = <0x340000 0x20000>;