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Commit 5144dbbc authored by Meng Wang's avatar Meng Wang Committed by Gerrit - the friendly Code Review server
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soc: swr-mstr: update component and interrupt enable sequence 



Enable component after enabling interrupt to avoid missing
some intterupt during master init.

Change-Id: I0f60c5431a815c58f878d3b9275a046e47939111
Signed-off-by: default avatarMeng Wang <mengw@codeaurora.org>
parent a1d9ad0e

soc/swr-mstr-ctrl.c

+3 −3
Original line number Diff line number Diff line
@@ -2489,9 +2489,6 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) 
	reg[len] = SWRM_COMP_CFG_ADDR;

	value[len++] = 0x02;



	reg[len] = SWRM_COMP_CFG_ADDR;

	value[len++] = 0x03;



	reg[len] = SWRM_INTERRUPT_CLEAR;

	value[len++] = 0xFFFFFFFF;
@@ -2503,6 +2500,9 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) 
	reg[len] = SWR_MSTR_RX_SWRM_CPU_INTERRUPT_EN;

	value[len++] = swrm->intr_mask;



	reg[len] = SWRM_COMP_CFG_ADDR;

	value[len++] = 0x03;



	swr_master_bulk_write(swrm, reg, value, len);



	if (!swrm_check_link_status(swrm, 0x1)) {