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Commit a1d9ad0e authored by Vatsal Bucha's avatar Vatsal Bucha
Browse files

ASoC: wcd937x: Add change for LDOL VOUT accuracy calibration 



ATE stores the calibration result in EFUSE register. This has to
be copied to sleep bandgap voltage for accurate calibration.

Change-Id: I118c5c3b42ba4cfd42185d8da6d468f44e31b88f
Signed-off-by: default avatarVatsal Bucha <vbucha@codeaurora.org>
parent 505430b7

asoc/codecs/wcd937x/wcd937x.c

+12 −1
Original line number Original line Diff line number Diff line
@@ -113,8 +113,19 @@ static int wcd937x_handle_post_irq(void *data) 




static int wcd937x_init_reg(struct snd_soc_component *component)

static int wcd937x_init_reg(struct snd_soc_component *component)

{

{

	u32 val =0;



	val = snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_29)

	     & 0x0F;

	if (snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16)

	    == 0x02 || snd_soc_component_read32(component,

	    WCD937X_DIGITAL_EFUSE_REG_17) > 0x09) {

		snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,

				0x0E, val);

	} else {

		snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,

		snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,

				0x0E, 0x0E);

				0x0E, 0x0E);

	}

	snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,

	snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL,

				0x80, 0x80);

				0x80, 0x80);

	usleep_range(1000, 1010);

	usleep_range(1000, 1010);