dwc3: core: Add ssp u3 u0 link state related quirk

USB PHY (qmp super speed phy) is unable to consistently move between
the u3 (p3)/u0(p0) states causing controller and phy link level issues
resulting in device re-enumeration. Fix the issue by forcing qmp phy to
move to P2 state always before moving to P0 from P3 state. Forcing by
phy link state is done by enabling Ux_exit_in_Px (BIT:27) and P3ExSigP2
(BIT:10) of GUSB3PIPECTL register.

Change-Id: I1edd6c77769d3139863413eed82f2b8b98b33d42
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>