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Commit 5019d7c8 authored by Todor Tomov's avatar Todor Tomov Committed by Mauro Carvalho Chehab
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media: camss: csid: MIPI10 to Plain16 format conversion



Use the PRDI mode on 8x96 to allow to configure RAW MIPI10
to Plain16 format conversion.

Signed-off-by: default avatarTodor Tomov <todor.tomov@linaro.org>
Signed-off-by: default avatarHans Verkuil <hansverk@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 7e37f47f
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+32 −1
Original line number Original line Diff line number Diff line
@@ -32,6 +32,15 @@
			(((v) == CAMSS_8x16 ? 0x010 : 0x014) + 0x4 * (n))
			(((v) == CAMSS_8x16 ? 0x010 : 0x014) + 0x4 * (n))
#define CAMSS_CSID_CID_n_CFG(v, n)	\
#define CAMSS_CSID_CID_n_CFG(v, n)	\
			(((v) == CAMSS_8x16 ? 0x020 : 0x024) + 0x4 * (n))
			(((v) == CAMSS_8x16 ? 0x020 : 0x024) + 0x4 * (n))
#define CAMSS_CSID_CID_n_CFG_ISPIF_EN	BIT(0)
#define CAMSS_CSID_CID_n_CFG_RDI_EN	BIT(1)
#define CAMSS_CSID_CID_n_CFG_DECODE_FORMAT_SHIFT	4
#define CAMSS_CSID_CID_n_CFG_PLAIN_FORMAT_8		(0 << 8)
#define CAMSS_CSID_CID_n_CFG_PLAIN_FORMAT_16		(1 << 8)
#define CAMSS_CSID_CID_n_CFG_PLAIN_ALIGNMENT_LSB	(0 << 9)
#define CAMSS_CSID_CID_n_CFG_PLAIN_ALIGNMENT_MSB	(1 << 9)
#define CAMSS_CSID_CID_n_CFG_RDI_MODE_RAW_DUMP		(0 << 10)
#define CAMSS_CSID_CID_n_CFG_RDI_MODE_PLAIN_PACKING	(1 << 10)
#define CAMSS_CSID_IRQ_CLEAR_CMD(v)	((v) == CAMSS_8x16 ? 0x060 : 0x064)
#define CAMSS_CSID_IRQ_CLEAR_CMD(v)	((v) == CAMSS_8x16 ? 0x060 : 0x064)
#define CAMSS_CSID_IRQ_MASK(v)		((v) == CAMSS_8x16 ? 0x064 : 0x068)
#define CAMSS_CSID_IRQ_MASK(v)		((v) == CAMSS_8x16 ? 0x064 : 0x068)
#define CAMSS_CSID_IRQ_STATUS(v)	((v) == CAMSS_8x16 ? 0x068 : 0x06c)
#define CAMSS_CSID_IRQ_STATUS(v)	((v) == CAMSS_8x16 ? 0x068 : 0x06c)
@@ -330,6 +339,16 @@ static u32 csid_src_pad_code(struct csid_device *csid, u32 sink_code,
		return sink_code;
		return sink_code;
	} else if (csid->camss->version == CAMSS_8x96) {
	} else if (csid->camss->version == CAMSS_8x96) {
		switch (sink_code) {
		switch (sink_code) {
		case MEDIA_BUS_FMT_SBGGR10_1X10:
		{
			u32 src_code[] = {
				MEDIA_BUS_FMT_SBGGR10_1X10,
				MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
			};

			return csid_find_code(src_code, ARRAY_SIZE(src_code),
					      index, src_req_code);
		}
		default:
		default:
			if (index > 0)
			if (index > 0)
				return 0;
				return 0;
@@ -636,7 +655,19 @@ static int csid_set_stream(struct v4l2_subdev *sd, int enable)
		writel_relaxed(val, csid->base +
		writel_relaxed(val, csid->base +
			       CAMSS_CSID_CID_LUT_VC_n(ver, vc));
			       CAMSS_CSID_CID_LUT_VC_n(ver, vc));


		val = (df << 4) | 0x3;
		val = CAMSS_CSID_CID_n_CFG_ISPIF_EN;
		val |= CAMSS_CSID_CID_n_CFG_RDI_EN;
		val |= df << CAMSS_CSID_CID_n_CFG_DECODE_FORMAT_SHIFT;
		val |= CAMSS_CSID_CID_n_CFG_RDI_MODE_RAW_DUMP;
		if (csid->camss->version == CAMSS_8x96 &&
			csid->fmt[MSM_CSID_PAD_SINK].code ==
					MEDIA_BUS_FMT_SBGGR10_1X10 &&
			csid->fmt[MSM_CSID_PAD_SRC].code ==
					MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
			val |= CAMSS_CSID_CID_n_CFG_RDI_MODE_PLAIN_PACKING;
			val |= CAMSS_CSID_CID_n_CFG_PLAIN_FORMAT_16;
			val |= CAMSS_CSID_CID_n_CFG_PLAIN_ALIGNMENT_LSB;
		}
		writel_relaxed(val, csid->base +
		writel_relaxed(val, csid->base +
			       CAMSS_CSID_CID_n_CFG(ver, cid));
			       CAMSS_CSID_CID_n_CFG(ver, cid));


+64 −0
Original line number Original line Diff line number Diff line
@@ -76,6 +76,13 @@
					(0x254 + 0x200 * (m) + 0x4 * (n))
					(0x254 + 0x200 * (m) + 0x4 * (n))
#define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n)	\
#define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n)	\
					(0x264 + 0x200 * (m) + 0x4 * (n))
					(0x264 + 0x200 * (m) + 0x4 * (n))
/* PACK_CFG registers are 8x96 only */
#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n)	\
					(0x270 + 0x200 * (m) + 0x4 * (n))
#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n)	\
					(0x27c + 0x200 * (m) + 0x4 * (n))
#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c)	\
					(1 << ((cid % 8) * 4))
#define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n)	\
#define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n)	\
					(0x2c0 + 0x200 * (m) + 0x4 * (n))
					(0x2c0 + 0x200 * (m) + 0x4 * (n))
#define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n)	\
#define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n)	\
@@ -128,6 +135,7 @@ static const u32 ispif_formats_8x96[] = {
	MEDIA_BUS_FMT_SGBRG10_1X10,
	MEDIA_BUS_FMT_SGBRG10_1X10,
	MEDIA_BUS_FMT_SGRBG10_1X10,
	MEDIA_BUS_FMT_SGRBG10_1X10,
	MEDIA_BUS_FMT_SRGGB10_1X10,
	MEDIA_BUS_FMT_SRGGB10_1X10,
	MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
	MEDIA_BUS_FMT_SBGGR12_1X12,
	MEDIA_BUS_FMT_SBGGR12_1X12,
	MEDIA_BUS_FMT_SGBRG12_1X12,
	MEDIA_BUS_FMT_SGBRG12_1X12,
	MEDIA_BUS_FMT_SGRBG12_1X12,
	MEDIA_BUS_FMT_SGRBG12_1X12,
@@ -666,6 +674,54 @@ static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf,
	writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
	writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
}
}


/*
 * ispif_config_pack - Config packing for PRDI mode
 * @ispif: ISPIF device
 * @code: media bus format code
 * @intf: VFE interface
 * @cid: desired CID to handle
 * @vfe: VFE HW module id
 * @enable: enable or disable
 */
static void ispif_config_pack(struct ispif_device *ispif, u32 code,
			      enum ispif_intf intf, u8 cid, u8 vfe, u8 enable)
{
	u32 addr, val;

	if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE)
		return;

	switch (intf) {
	case RDI0:
		if (cid < 8)
			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0);
		else
			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0);
		break;
	case RDI1:
		if (cid < 8)
			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1);
		else
			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1);
		break;
	case RDI2:
		if (cid < 8)
			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2);
		else
			addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2);
		break;
	default:
		return;
	}

	if (enable)
		val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid);
	else
		val = 0;

	writel_relaxed(val, ispif->base + addr);
}

/*
/*
 * ispif_set_intf_cmd - Set command to enable/disable interface
 * ispif_set_intf_cmd - Set command to enable/disable interface
 * @ispif: ISPIF device
 * @ispif: ISPIF device
@@ -734,6 +790,10 @@ static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
		ispif_select_csid(ispif, intf, csid, vfe, 1);
		ispif_select_csid(ispif, intf, csid, vfe, 1);
		ispif_select_cid(ispif, intf, cid, vfe, 1);
		ispif_select_cid(ispif, intf, cid, vfe, 1);
		ispif_config_irq(ispif, intf, vfe, 1);
		ispif_config_irq(ispif, intf, vfe, 1);
		if (to_camss(ispif)->version == CAMSS_8x96)
			ispif_config_pack(ispif,
					  line->fmt[MSM_ISPIF_PAD_SINK].code,
					  intf, cid, vfe, 1);
		ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,
		ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,
				   intf, vfe, vc);
				   intf, vfe, vc);
	} else {
	} else {
@@ -747,6 +807,10 @@ static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
			return ret;
			return ret;


		mutex_lock(&ispif->config_lock);
		mutex_lock(&ispif->config_lock);
		if (to_camss(ispif)->version == CAMSS_8x96)
			ispif_config_pack(ispif,
					  line->fmt[MSM_ISPIF_PAD_SINK].code,
					  intf, cid, vfe, 0);
		ispif_config_irq(ispif, intf, vfe, 0);
		ispif_config_irq(ispif, intf, vfe, 0);
		ispif_select_cid(ispif, intf, cid, vfe, 0);
		ispif_select_cid(ispif, intf, cid, vfe, 0);
		ispif_select_csid(ispif, intf, csid, vfe, 0);
		ispif_select_csid(ispif, intf, csid, vfe, 0);
+1 −0
Original line number Original line Diff line number Diff line
@@ -89,6 +89,7 @@ static const struct vfe_format formats_rdi_8x96[] = {
	{ MEDIA_BUS_FMT_SGBRG10_1X10, 10 },
	{ MEDIA_BUS_FMT_SGBRG10_1X10, 10 },
	{ MEDIA_BUS_FMT_SGRBG10_1X10, 10 },
	{ MEDIA_BUS_FMT_SGRBG10_1X10, 10 },
	{ MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
	{ MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
	{ MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, 16 },
	{ MEDIA_BUS_FMT_SBGGR12_1X12, 12 },
	{ MEDIA_BUS_FMT_SBGGR12_1X12, 12 },
	{ MEDIA_BUS_FMT_SGBRG12_1X12, 12 },
	{ MEDIA_BUS_FMT_SGBRG12_1X12, 12 },
	{ MEDIA_BUS_FMT_SGRBG12_1X12, 12 },
	{ MEDIA_BUS_FMT_SGRBG12_1X12, 12 },
+2 −0
Original line number Original line Diff line number Diff line
@@ -101,6 +101,8 @@ static const struct camss_format_info formats_rdi_8x96[] = {
	  { { 1, 1 } }, { { 1, 1 } }, { 10 } },
	  { { 1, 1 } }, { { 1, 1 } }, { 10 } },
	{ MEDIA_BUS_FMT_SRGGB10_1X10, V4L2_PIX_FMT_SRGGB10P, 1,
	{ MEDIA_BUS_FMT_SRGGB10_1X10, V4L2_PIX_FMT_SRGGB10P, 1,
	  { { 1, 1 } }, { { 1, 1 } }, { 10 } },
	  { { 1, 1 } }, { { 1, 1 } }, { 10 } },
	{ MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_PIX_FMT_SBGGR10, 1,
	  { { 1, 1 } }, { { 1, 1 } }, { 16 } },
	{ MEDIA_BUS_FMT_SBGGR12_1X12, V4L2_PIX_FMT_SBGGR12P, 1,
	{ MEDIA_BUS_FMT_SBGGR12_1X12, V4L2_PIX_FMT_SBGGR12P, 1,
	  { { 1, 1 } }, { { 1, 1 } }, { 12 } },
	  { { 1, 1 } }, { { 1, 1 } }, { 12 } },
	{ MEDIA_BUS_FMT_SGBRG12_1X12, V4L2_PIX_FMT_SGBRG12P, 1,
	{ MEDIA_BUS_FMT_SGBRG12_1X12, V4L2_PIX_FMT_SGBRG12P, 1,