Donate to
e Foundation
|
Murena
handsets with /e/OS | Own a part of Murena!
Learn more
Skip to content
GitLab
Explore
Sign in
Register
Commit
4ecdbf7a
authored
Jan 28, 2019
by
qctecmdr Service
Committed by
Gerrit - the friendly Code Review server
Jan 28, 2019
Browse files
Merge "clk: Move VDD voltage voting from core clock to top clock"
parents
80ac3620
61dad289
Loading
Loading
Loading
Changes
1
Hide whitespace changes
Inline
Side-by-side
Loading
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment