Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4c495c20 authored by Mikko Perttunen's avatar Mikko Perttunen Committed by Peter De Schrijver
Browse files

clk: tegra124: Add PLL_M_UD and PLL_C_UD clocks 



These clocks are used as parents for some EMC timings.

Signed-off-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
parent d364a77d

drivers/clk/tegra/clk-tegra124.c

+8 −0
Original line number Diff line number Diff line
@@ -1166,6 +1166,12 @@ static void __init tegra124_pll_init(void __iomem *clk_base, 
	clk_register_clkdev(clk, "pll_c_out1", NULL);

	clks[TEGRA124_CLK_PLL_C_OUT1] = clk;



	/* PLLC_UD */

	clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",

					CLK_SET_RATE_PARENT, 1, 1);

	clk_register_clkdev(clk, "pll_c_ud", NULL);

	clks[TEGRA124_CLK_PLL_C_UD] = clk;



	/* PLLC2 */

	clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,

			     &pll_c2_params, NULL);
@@ -1198,6 +1204,8 @@ static void __init tegra124_pll_init(void __iomem *clk_base, 
	/* PLLM_UD */

	clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",

					CLK_SET_RATE_PARENT, 1, 1);

	clk_register_clkdev(clk, "pll_m_ud", NULL);

	clks[TEGRA124_CLK_PLL_M_UD] = clk;



	/* PLLU */

	val = readl(clk_base + pll_u_params.base_reg);