Merge branch 'drm-intel-fixes' into drm-intel-next (46168f39) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/drm/i915/i915_drv.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -1269,6 +1269,7 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove

		#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
		#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
		#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)

		#define PRIMARY_RINGBUFFER_SIZE (128*1024)

drivers/gpu/drm/i915/i915_suspend.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -862,8 +862,10 @@ int i915_restore_state(struct drm_device *dev)
		/* Clock gating state */
		intel_init_clock_gating(dev);

		if (HAS_PCH_SPLIT(dev))
		if (HAS_PCH_SPLIT(dev)) {
		ironlake_enable_drps(dev);
		intel_init_emon(dev);
		}

		/* Cache mode state */
		I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 \| 0xffff0000);

drivers/gpu/drm/i915/intel_display.c

+37 −24

Original line number	Diff line number	Diff line
		@@ -1683,6 +1683,37 @@ static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
		udelay(500);
		}

		static void intel_fdi_normal_train(struct drm_crtc *crtc)
		{
		struct drm_device *dev = crtc->dev;
		struct drm_i915_private *dev_priv = dev->dev_private;
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		int pipe = intel_crtc->pipe;
		u32 reg, temp;

		/* enable normal train */
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		I915_WRITE(reg, temp);

		reg = FDI_RX_CTL(pipe);
		temp = I915_READ(reg);
		if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp \|= FDI_LINK_TRAIN_NONE;
		}
		I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);

		/* wait one idle pattern time */
		POSTING_READ(reg);
		udelay(1000);
		}

		/* The FDI link training functions for ILK/Ibexpeak. */
		static void ironlake_fdi_link_train(struct drm_crtc *crtc)
		{
		@@ -1769,27 +1800,6 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)

		DRM_DEBUG_KMS("FDI train done\n");

		/* enable normal train */
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp \|= FDI_LINK_TRAIN_NONE \| FDI_TX_ENHANCE_FRAME_ENABLE;
		I915_WRITE(reg, temp);

		reg = FDI_RX_CTL(pipe);
		temp = I915_READ(reg);
		if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp \|= FDI_LINK_TRAIN_NORMAL_CPT;
		} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp \|= FDI_LINK_TRAIN_NONE;
		}
		I915_WRITE(reg, temp \| FDI_RX_ENHANCE_FRAME_ENABLE);

		/* wait one idle pattern time */
		POSTING_READ(reg);
		udelay(1000);
		}

		static const int const snb_b_fdi_train_param [] = {
		@@ -2092,6 +2102,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
		I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
		I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));

		intel_fdi_normal_train(crtc);

		/* For PCH DP, enable TRANS_DP_CTL */
		if (HAS_PCH_CPT(dev) &&
		intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		@@ -2202,6 +2214,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
		udelay(100);

		/* Ironlake workaround, disable clock pointer after downing FDI */
		if (HAS_PCH_IBX(dev))
		I915_WRITE(FDI_RX_CHICKEN(pipe),
		I915_READ(FDI_RX_CHICKEN(pipe) &
		~FDI_RX_PHASE_SYNC_POINTER_ENABLE));

drivers/gpu/drm/i915/intel_drv.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -296,6 +296,7 @@ extern void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		extern void intel_init_clock_gating(struct drm_device *dev);
		extern void ironlake_enable_drps(struct drm_device *dev);
		extern void ironlake_disable_drps(struct drm_device *dev);
		extern void intel_init_emon(struct drm_device *dev);

		extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
		struct drm_gem_object *obj,