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Commit 16a02cf0 authored by Zhenyu Wang's avatar Zhenyu Wang Committed by Chris Wilson
Browse files

agp/intel: fix cache control for sandybridge 



This is broken from 97ef1bdd.
Let's set the correct bit for LLC+MLC and LLC only.

Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 8d0f5670

drivers/char/agp/intel-gtt.c

+2 −2
Original line number Diff line number Diff line
@@ -1213,11 +1213,11 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry, 
	if (type_mask == AGP_USER_MEMORY)

		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;

	else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {

		pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;

		pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	} else { /* set 'normal'/'cached' to LLC by default */

		pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;

		pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	}