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Commit 46134f59 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add support for GDSCs on Lito"

parents 846dbfa1 e2f0ad31

arch/arm64/boot/dts/qcom/lito-gdsc.dtsi

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 */



&soc {

	/* GCC GDSCs */

	ufs_phy_gdsc: qcom,gdsc@177004 {

		compatible = "regulator-fixed";

		reg = <0x177004 0x4>;

		regulator-name = "ufs_phy_gdsc";

	};



	usb30_prim_gdsc: qcom,gdsc@10f004 {

		compatible = "regulator-fixed";

		reg = <0x10f004 0x4>;

		regulator-name = "usb30_prim_gdsc";

	};



	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {

		compatible = "regulator-fixed";

		reg = <0x17d050 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

	};



	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {

		compatible = "regulator-fixed";

		reg = <0x17d058 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

	};



	hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {

		compatible = "regulator-fixed";

		reg = <0x17d054 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

	};



	/* CAM_CC GDSCs */

	bps_gdsc: qcom,gdsc@ad07004 {

		compatible = "regulator-fixed";

		reg = <0xad07004 0x4>;

		regulator-name = "bps_gdsc";

	};



	ipe_0_gdsc: qcom,gdsc@ad08004 {

		compatible = "regulator-fixed";

		reg = <0xad08004 0x4>;

		regulator-name = "ipe_0_gdsc";

	};



	ipe_1_gdsc: qcom,gdsc@ad09004 {

		compatible = "regulator-fixed";

		reg = <0xad09004 0x4>;

		regulator-name = "ipe_1_gdsc";

	};



	ife_0_gdsc: qcom,gdsc@ad0a004 {

		compatible = "regulator-fixed";

		reg = <0xad0a004 0x4>;

		regulator-name = "ife_0_gdsc";

	};



	ife_1_gdsc: qcom,gdsc@ad0b004 {

		compatible = "regulator-fixed";

		reg = <0xad0b004 0x4>;

		regulator-name = "ife_1_gdsc";

	};



	titan_top_gdsc: qcom,gdsc@ad0c1c4 {

		compatible = "regulator-fixed";

		reg = <0xad0c1c4 0x4>;

		regulator-name = "titan_top_gdsc";

	};



	/* DISP_CC GDSC */

	mdss_core_gdsc: qcom,gdsc@af03000 {

		compatible = "regulator-fixed";

		reg = <0xaf03000 0x4>;

		regulator-name = "mdss_core_gdsc";

	};



	/* GPU_CC GDSCs */

	gpu_cx_hw_ctrl: syscon@3d91540 {

		compatible = "syscon";

		reg = <0x3d91540 0x4>;

	};



	gpu_cx_gdsc: qcom,gdsc@3d9106c {

		compatible = "regulator-fixed";

		reg = <0x3d9106c 0x4>;

		regulator-name = "gpu_cx_gdsc";

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;

		qcom,no-status-check-on-disable;

		qcom,clk-dis-wait-val = <8>;

		qcom,gds-timeout = <500>;

	};



	gpu_gx_domain_addr: syscon@3d91508 {

		compatible = "syscon";

		reg = <0x3d91508 0x4>;

	};



	gpu_gx_sw_reset: syscon@3d91008 {

		compatible = "syscon";

		reg = <0x3d91008 0x4>;

	};



	gpu_gx_gdsc: qcom,gdsc@3d9100c {

		compatible = "regulator-fixed";

		reg = <0x3d9100c 0x4>;

		regulator-name = "gpu_gx_gdsc";

		domain-addr = <&gpu_gx_domain_addr>;

		sw-reset = <&gpu_gx_sw_reset>;

		qcom,reset-aon-logic;

	};



	/* NPU GDSC */

	npu_core_gdsc: qcom,gdsc@9981004 {

		compatible = "regulator-fixed";

		reg = <0x9981004 0x4>;

		regulator-name = "npu_core_gdsc";

	};



	/* VIDEO_CC GDSCs */

	mvsc_gdsc: qcom,gdsc@ab00814 {

		compatible = "regulator-fixed";

		reg = <0xab00814 0x4>;

		regulator-name = "mvsc_gdsc";

	};



	mvs0_gdsc: qcom,gdsc@ab00874 {

		compatible = "regulator-fixed";

		reg = <0xab00874 0x4>;

		regulator-name = "mvs0_gdsc";

	};



	mvs1_gdsc: qcom,gdsc@ab008b4 {

		compatible = "regulator-fixed";

		reg = <0xab008b4 0x4>;

		regulator-name = "mvs1_gdsc";

	};

};

include/dt-bindings/clock/qcom,camcc-lito.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */



#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_LITO_H

#define _DT_BINDINGS_CLK_QCOM_CAM_CC_LITO_H



#define CAM_CC_PLL0						0

#define CAM_CC_PLL0_OUT_EVEN					1

#define CAM_CC_PLL0_OUT_ODD					2

#define CAM_CC_PLL1						3

#define CAM_CC_PLL1_OUT_EVEN					4

#define CAM_CC_PLL2						5

#define CAM_CC_PLL2_OUT_AUX					6

#define CAM_CC_PLL2_OUT_MAIN					7

#define CAM_CC_PLL3						8

#define CAM_CC_PLL3_OUT_EVEN					9

#define CAM_CC_PLL4						10

#define CAM_CC_PLL4_OUT_EVEN					11

#define CAM_CC_CORE_AHB_CLK					12

#define CAM_CC_CPAS_AHB_CLK					13

#define CAM_CC_CPHY_RX_CLK_SRC					14

#define CAM_CC_CSI0PHYTIMER_CLK					15

#define CAM_CC_CSI0PHYTIMER_CLK_SRC				16

#define CAM_CC_CSI1PHYTIMER_CLK					17

#define CAM_CC_CSI1PHYTIMER_CLK_SRC				18

#define CAM_CC_CSI2PHYTIMER_CLK					19

#define CAM_CC_CSI2PHYTIMER_CLK_SRC				20

#define CAM_CC_CSI3PHYTIMER_CLK					21

#define CAM_CC_CSI3PHYTIMER_CLK_SRC				22

#define CAM_CC_CSIPHY0_CLK					23

#define CAM_CC_CSIPHY1_CLK					24

#define CAM_CC_CSIPHY2_CLK					25

#define CAM_CC_CSIPHY3_CLK					26

#define CAM_CC_FAST_AHB_CLK_SRC					27

#define CAM_CC_FD_CORE_CLK					28

#define CAM_CC_FD_CORE_CLK_SRC					29

#define CAM_CC_FD_CORE_UAR_CLK					30

#define CAM_CC_GDSC_CLK						31

#define CAM_CC_ICP_AHB_CLK					32

#define CAM_CC_ICP_CLK						33

#define CAM_CC_ICP_CLK_SRC					34

#define CAM_CC_IFE_0_AXI_CLK					35

#define CAM_CC_IFE_0_CLK					36

#define CAM_CC_IFE_0_CLK_SRC					37

#define CAM_CC_IFE_0_CPHY_RX_CLK				38

#define CAM_CC_IFE_0_CSID_CLK					39

#define CAM_CC_IFE_0_CSID_CLK_SRC				40

#define CAM_CC_IFE_0_DSP_CLK					41

#define CAM_CC_IFE_1_AXI_CLK					42

#define CAM_CC_IFE_1_CLK					43

#define CAM_CC_IFE_1_CLK_SRC					44

#define CAM_CC_IFE_1_CPHY_RX_CLK				45

#define CAM_CC_IFE_1_CSID_CLK					46

#define CAM_CC_IFE_1_CSID_CLK_SRC				47

#define CAM_CC_IFE_1_DSP_CLK					48

#define CAM_CC_IFE_LITE_CLK					49

#define CAM_CC_IFE_LITE_CLK_SRC					50

#define CAM_CC_IFE_LITE_CPHY_RX_CLK				51

#define CAM_CC_IFE_LITE_CSID_CLK				52

#define CAM_CC_IFE_LITE_CSID_CLK_SRC				53

#define CAM_CC_IPE_0_AHB_CLK					54

#define CAM_CC_IPE_0_AREG_CLK					55

#define CAM_CC_IPE_0_AXI_CLK					56

#define CAM_CC_IPE_0_CLK					57

#define CAM_CC_IPE_0_CLK_SRC					58

#define CAM_CC_IPE_1_AHB_CLK					59

#define CAM_CC_IPE_1_AREG_CLK					60

#define CAM_CC_IPE_1_AXI_CLK					61

#define CAM_CC_IPE_1_CLK					62

#define CAM_CC_JPEG_CLK						63

#define CAM_CC_JPEG_CLK_SRC					64

#define CAM_CC_LRME_CLK						65

#define CAM_CC_LRME_CLK_SRC					66

#define CAM_CC_MCLK0_CLK					67

#define CAM_CC_MCLK0_CLK_SRC					68

#define CAM_CC_MCLK1_CLK					69

#define CAM_CC_MCLK1_CLK_SRC					70

#define CAM_CC_MCLK2_CLK					71

#define CAM_CC_MCLK2_CLK_SRC					72

#define CAM_CC_MCLK3_CLK					73

#define CAM_CC_MCLK3_CLK_SRC					74

#define CAM_CC_BPS_AHB_CLK					75

#define CAM_CC_BPS_AREG_CLK					76

#define CAM_CC_BPS_AXI_CLK					77

#define CAM_CC_BPS_CLK						78

#define CAM_CC_BPS_CLK_SRC					79

#define CAM_CC_CAMNOC_AXI_CLK					80

#define CAM_CC_CAMNOC_AXI_CLK_SRC				81

#define CAM_CC_CAMNOC_DCD_XO_CLK				82

#define CAM_CC_CCI_0_CLK					83

#define CAM_CC_CCI_0_CLK_SRC					84

#define CAM_CC_CCI_1_CLK					85

#define CAM_CC_CCI_1_CLK_SRC					86

#define CAM_CC_SLOW_AHB_CLK_SRC					87

#define CAM_CC_XO_CLK_SRC					88



#endif

include/dt-bindings/clock/qcom,dispcc-lito.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */



#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_LITO_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_LITO_H



#define DISP_CC_PLL0						0

#define DISP_CC_MDSS_AHB_CLK_SRC				1

#define DISP_CC_MDSS_BYTE0_CLK					2

#define DISP_CC_MDSS_BYTE0_CLK_SRC				3

#define DISP_CC_MDSS_BYTE0_INTF_CLK				4

#define DISP_CC_MDSS_BYTE1_CLK					5

#define DISP_CC_MDSS_BYTE1_CLK_SRC				6

#define DISP_CC_MDSS_BYTE1_INTF_CLK				7

#define DISP_CC_MDSS_DP_AUX_CLK					8

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				9

#define DISP_CC_MDSS_DP_CRYPTO_CLK				10

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				11

#define DISP_CC_MDSS_DP_LINK_CLK				12

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				13

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				14

#define DISP_CC_MDSS_DP_PIXEL1_CLK				15

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				16

#define DISP_CC_MDSS_DP_PIXEL_CLK				17

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				18

#define DISP_CC_MDSS_ESC0_CLK					19

#define DISP_CC_MDSS_ESC0_CLK_SRC				20

#define DISP_CC_MDSS_ESC1_CLK					21

#define DISP_CC_MDSS_ESC1_CLK_SRC				22

#define DISP_CC_MDSS_MDP_CLK					23

#define DISP_CC_MDSS_MDP_CLK_SRC				24

#define DISP_CC_MDSS_MDP_LUT_CLK				25

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				26

#define DISP_CC_MDSS_PCLK0_CLK					27

#define DISP_CC_MDSS_PCLK0_CLK_SRC				28

#define DISP_CC_MDSS_PCLK1_CLK					29

#define DISP_CC_MDSS_PCLK1_CLK_SRC				30

#define DISP_CC_MDSS_ROT_CLK					31

#define DISP_CC_MDSS_ROT_CLK_SRC				32

#define DISP_CC_MDSS_RSCC_AHB_CLK				33

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				34

#define DISP_CC_MDSS_VSYNC_CLK					35

#define DISP_CC_MDSS_VSYNC_CLK_SRC				36

#define DISP_CC_MDSS_AHB_CLK					37

#define DISP_CC_XO_CLK						38

#define DISP_CC_XO_CLK_SRC					39



#endif

include/dt-bindings/clock/qcom,gcc-lito.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */



#ifndef _DT_BINDINGS_CLK_QCOM_GCC_LITO_H

#define _DT_BINDINGS_CLK_QCOM_GCC_LITO_H



#define GPLL0							0

#define GPLL0_OUT_EVEN						1

#define GPLL6							2

#define GPLL9							3

#define GCC_CAMERA_HF_AXI_CLK					4

#define GCC_CAMERA_SF_AXI_CLK					5

#define GCC_CAMERA_THROTTLE_HF_AXI_CLK				6

#define GCC_CAMERA_THROTTLE_SF_AXI_CLK				7

#define GCC_CAMERA_XO_CLK					8

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				9

#define GCC_CPUSS_AHB_CLK					10

#define GCC_CPUSS_AHB_CLK_SRC					11

#define GCC_CPUSS_GNOC_CLK					12

#define GCC_CPUSS_RBCPR_CLK					13

#define GCC_DDRSS_GPU_AXI_CLK					14

#define GCC_DISP_AHB_CLK					15

#define GCC_DISP_GPLL0_CLK_SRC					16

#define GCC_DISP_HF_AXI_CLK					17

#define GCC_DISP_SF_AXI_CLK					18

#define GCC_DISP_THROTTLE_HF_AXI_CLK				19

#define GCC_DISP_THROTTLE_SF_AXI_CLK				20

#define GCC_DISP_XO_CLK						21

#define GCC_DPM_AHB_CLK						22

#define GCC_DPM_CLK						23

#define GCC_DPM_CLK_SRC						24

#define GCC_GP1_CLK						25

#define GCC_GP1_CLK_SRC						26

#define GCC_GP2_CLK						27

#define GCC_GP2_CLK_SRC						28

#define GCC_GP3_CLK						29

#define GCC_GP3_CLK_SRC						30

#define GCC_GPU_CFG_AHB_CLK					31

#define GCC_GPU_GPLL0_CLK_SRC					32

#define GCC_GPU_GPLL0_DIV_CLK_SRC				33

#define GCC_GPU_IREF_CLK					34

#define GCC_GPU_MEMNOC_GFX_CLK					35

#define GCC_GPU_SNOC_DVM_GFX_CLK				36

#define GCC_NPU_AXI_CLK						37

#define GCC_NPU_BWMON2_AXI_CLK					38

#define GCC_NPU_BWMON_AXI_CLK					39

#define GCC_NPU_BWMON_CFG_AHB_CLK				40

#define GCC_NPU_CFG_AHB_CLK					41

#define GCC_NPU_DMA_CLK						42

#define GCC_NPU_GPLL0_CLK_SRC					43

#define GCC_NPU_GPLL0_DIV_CLK_SRC				44

#define GCC_PDM2_CLK						45

#define GCC_PDM2_CLK_SRC					46

#define GCC_PDM_AHB_CLK						47

#define GCC_PDM_XO4_CLK						48

#define GCC_PRNG_AHB_CLK					49

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				50

#define GCC_QMIP_CAMERA_RT_AHB_CLK				51

#define GCC_QMIP_DISP_AHB_CLK					52

#define GCC_QMIP_RT_DISP_AHB_CLK				53

#define GCC_QMIP_VIDEO_CVP_AHB_CLK				54

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				55

#define GCC_QUPV3_WRAP0_S0_CLK					56

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				57

#define GCC_QUPV3_WRAP0_S1_CLK					58

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				59

#define GCC_QUPV3_WRAP0_S2_CLK					60

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				61

#define GCC_QUPV3_WRAP0_S3_CLK					62

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				63

#define GCC_QUPV3_WRAP0_S4_CLK					64

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				65

#define GCC_QUPV3_WRAP0_S5_CLK					66

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				67

#define GCC_QUPV3_WRAP1_S0_CLK					68

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				69

#define GCC_QUPV3_WRAP1_S1_CLK					70

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				71

#define GCC_QUPV3_WRAP1_S2_CLK					72

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				73

#define GCC_QUPV3_WRAP1_S3_CLK					74

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				75

#define GCC_QUPV3_WRAP1_S4_CLK					76

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				77

#define GCC_QUPV3_WRAP1_S5_CLK					78

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				79

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				80

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				81

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				82

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				83

#define GCC_SDCC1_AHB_CLK					84

#define GCC_SDCC1_APPS_CLK					85

#define GCC_SDCC1_APPS_CLK_SRC					86

#define GCC_SDCC1_ICE_CORE_CLK					87

#define GCC_SDCC1_ICE_CORE_CLK_SRC				88

#define GCC_SDCC2_AHB_CLK					89

#define GCC_SDCC2_APPS_CLK					90

#define GCC_SDCC2_APPS_CLK_SRC					91

#define GCC_SDCC4_AHB_CLK					92

#define GCC_SDCC4_APPS_CLK					93

#define GCC_SDCC4_APPS_CLK_SRC					94

#define GCC_SYS_NOC_CPUSS_AHB_CLK				95

#define GCC_UFS_1X_CLKREF_CLK					96

#define GCC_UFS_PHY_AHB_CLK					97

#define GCC_UFS_PHY_AXI_CLK					98

#define GCC_UFS_PHY_AXI_CLK_SRC					99

#define GCC_UFS_PHY_ICE_CORE_CLK				100

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				101

#define GCC_UFS_PHY_PHY_AUX_CLK					102

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				103

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				104

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				105

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				106

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				107

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				108

#define GCC_USB30_PRIM_MASTER_CLK				109

#define GCC_USB30_PRIM_MASTER_CLK_SRC				110

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				111

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			112

#define GCC_USB30_PRIM_SLEEP_CLK				113

#define GCC_USB3_PRIM_PHY_AUX_CLK				114

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				115

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				116

#define GCC_USB3_PRIM_PHY_PIPE_CLK				117

#define GCC_VIDEO_AHB_CLK					118

#define GCC_VIDEO_AXI_CLK					119

#define GCC_VIDEO_THROTTLE1_AXI_CLK				120

#define GCC_VIDEO_THROTTLE_AXI_CLK				121

#define GCC_VIDEO_XO_CLK					122

#define GCC_AGGRE_UFS_PHY_AXI_CLK				123

#define GCC_AGGRE_USB3_PRIM_AXI_CLK				124

#define GCC_BOOT_ROM_AHB_CLK					125

#define GCC_CAMERA_AHB_CLK					126



#define GCC_DPM_BCR						0

#define GCC_GPU_BCR						1

#define GCC_MMSS_BCR						2

#define GCC_NPU_BWMON_BCR					3

#define GCC_NPU_BCR						4

#define GCC_PDM_BCR						5

#define GCC_PRNG_BCR						6

#define GCC_QUPV3_WRAPPER_0_BCR					7

#define GCC_QUPV3_WRAPPER_1_BCR					8

#define GCC_SDCC1_BCR						9

#define GCC_SDCC2_BCR						10

#define GCC_SDCC4_BCR						11

#define GCC_UFS_PHY_BCR						12

#define GCC_USB30_PRIM_BCR					13

#define GCC_USB_PHY_CFG_AHB2PHY_BCR				14



#endif

include/dt-bindings/clock/qcom,gpucc-lito.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */



#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_LITO_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_LITO_H



#define GPU_CC_PLL0						0

#define GPU_CC_PLL0_OUT_EVEN					1

#define GPU_CC_PLL1						2

#define GPU_CC_CX_GFX3D_CLK					3

#define GPU_CC_CX_GFX3D_SLV_CLK					4

#define GPU_CC_CX_GMU_CLK					5

#define GPU_CC_CX_SNOC_DVM_CLK					6

#define GPU_CC_CXO_AON_CLK					7

#define GPU_CC_CXO_CLK						8

#define GPU_CC_GMU_CLK_SRC					9

#define GPU_CC_GX_CXO_CLK					10

#define GPU_CC_GX_GFX3D_CLK					11

#define GPU_CC_GX_GFX3D_CLK_SRC					12

#define GPU_CC_GX_GMU_CLK					13

#define GPU_CC_GX_VSENSE_CLK					14

#define GPU_CC_AHB_CLK						15

#define GPU_CC_CRC_AHB_CLK					16

#define GPU_CC_CX_APB_CLK					17

#define GPU_CC_RBCPR_AHB_CLK					18

#define GPU_CC_RBCPR_CLK					19

#define GPU_CC_RBCPR_CLK_SRC					20



#endif