Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e2f0ad31 authored by Taniya Das's avatar Taniya Das
Browse files

ARM: dts: msm: Add support for GDSCs on Lito 



Add all the GDSC footswitches supported on Lito for the clients to request
to enable/disable.

Change-Id: Idcd96613fce22df286c4771271877124e1aeeaa8
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 2032d330

arch/arm64/boot/dts/qcom/lito-gdsc.dtsi

0 → 100644
+148 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 */



&soc {

	/* GCC GDSCs */

	ufs_phy_gdsc: qcom,gdsc@177004 {

		compatible = "regulator-fixed";

		reg = <0x177004 0x4>;

		regulator-name = "ufs_phy_gdsc";

	};



	usb30_prim_gdsc: qcom,gdsc@10f004 {

		compatible = "regulator-fixed";

		reg = <0x10f004 0x4>;

		regulator-name = "usb30_prim_gdsc";

	};



	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {

		compatible = "regulator-fixed";

		reg = <0x17d050 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

	};



	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {

		compatible = "regulator-fixed";

		reg = <0x17d058 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

	};



	hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {

		compatible = "regulator-fixed";

		reg = <0x17d054 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

	};



	/* CAM_CC GDSCs */

	bps_gdsc: qcom,gdsc@ad07004 {

		compatible = "regulator-fixed";

		reg = <0xad07004 0x4>;

		regulator-name = "bps_gdsc";

	};



	ipe_0_gdsc: qcom,gdsc@ad08004 {

		compatible = "regulator-fixed";

		reg = <0xad08004 0x4>;

		regulator-name = "ipe_0_gdsc";

	};



	ipe_1_gdsc: qcom,gdsc@ad09004 {

		compatible = "regulator-fixed";

		reg = <0xad09004 0x4>;

		regulator-name = "ipe_1_gdsc";

	};



	ife_0_gdsc: qcom,gdsc@ad0a004 {

		compatible = "regulator-fixed";

		reg = <0xad0a004 0x4>;

		regulator-name = "ife_0_gdsc";

	};



	ife_1_gdsc: qcom,gdsc@ad0b004 {

		compatible = "regulator-fixed";

		reg = <0xad0b004 0x4>;

		regulator-name = "ife_1_gdsc";

	};



	titan_top_gdsc: qcom,gdsc@ad0c1c4 {

		compatible = "regulator-fixed";

		reg = <0xad0c1c4 0x4>;

		regulator-name = "titan_top_gdsc";

	};



	/* DISP_CC GDSC */

	mdss_core_gdsc: qcom,gdsc@af03000 {

		compatible = "regulator-fixed";

		reg = <0xaf03000 0x4>;

		regulator-name = "mdss_core_gdsc";

	};



	/* GPU_CC GDSCs */

	gpu_cx_hw_ctrl: syscon@3d91540 {

		compatible = "syscon";

		reg = <0x3d91540 0x4>;

	};



	gpu_cx_gdsc: qcom,gdsc@3d9106c {

		compatible = "regulator-fixed";

		reg = <0x3d9106c 0x4>;

		regulator-name = "gpu_cx_gdsc";

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;

		qcom,no-status-check-on-disable;

		qcom,clk-dis-wait-val = <8>;

		qcom,gds-timeout = <500>;

	};



	gpu_gx_domain_addr: syscon@3d91508 {

		compatible = "syscon";

		reg = <0x3d91508 0x4>;

	};



	gpu_gx_sw_reset: syscon@3d91008 {

		compatible = "syscon";

		reg = <0x3d91008 0x4>;

	};



	gpu_gx_gdsc: qcom,gdsc@3d9100c {

		compatible = "regulator-fixed";

		reg = <0x3d9100c 0x4>;

		regulator-name = "gpu_gx_gdsc";

		domain-addr = <&gpu_gx_domain_addr>;

		sw-reset = <&gpu_gx_sw_reset>;

		qcom,reset-aon-logic;

	};



	/* NPU GDSC */

	npu_core_gdsc: qcom,gdsc@9981004 {

		compatible = "regulator-fixed";

		reg = <0x9981004 0x4>;

		regulator-name = "npu_core_gdsc";

	};



	/* VIDEO_CC GDSCs */

	mvsc_gdsc: qcom,gdsc@ab00814 {

		compatible = "regulator-fixed";

		reg = <0xab00814 0x4>;

		regulator-name = "mvsc_gdsc";

	};



	mvs0_gdsc: qcom,gdsc@ab00874 {

		compatible = "regulator-fixed";

		reg = <0xab00874 0x4>;

		regulator-name = "mvs0_gdsc";

	};



	mvs1_gdsc: qcom,gdsc@ab008b4 {

		compatible = "regulator-fixed";

		reg = <0xab008b4 0x4>;

		regulator-name = "mvs1_gdsc";

	};

};