Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 44991eb4 authored by Jisheng Zhang's avatar Jisheng Zhang Committed by Sebastian Hesselbarth
Browse files

ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles 



For all BG2Q SoCs, 2 cycles is the best/correct value.

Signed-off-by: default avatarJisheng Zhang <jszhang@marvell.com>
Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
parent 7171511e
Show whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment