Merge "gpu/documentation: Update the bindings for bus frequencies"

				This value indicates which qcom,gpu-pwrlevel

				to jump on in case of context aware power level

				jump.

Properties:

Required Properties:

- reg:				Index of the powerlevel (0 = highest perf)

- qcom,gpu-freq			GPU frequency for the powerlevel (in Hz)

- qcom,bus-freq			Index to a bus level (defined by the bus

				settings)

				settings).

- qcom,bus-freq-ddrX		If specified, define the DDR specific bus

				frequency for the power level.  X will be the

				return value from of_fdt_get_ddrtype().

Optional Properties:

- qcom,bus-min			Minimum bus level to set for the power level

- qcom,bus-min-ddrX		If specified, define the DDR specific minimum

				bus level for the power level.  X will be the

				return value from of_fdt_get_ddrtype().

- qcom,bus-max			maximum bus level to set for the power level

- qcom,bus-max-ddrX		If specified, define the DDR specific maximum

				bus level for the power level.  X will be the

				return value from of_fdt_get_ddrtype().

- qcom,dvm-val:			Value that is used as a register setting for

				the ACD power feature. It helps determine the

				threshold for when ACD activates. 0xFFFFFFFF

	qcom,bus-max = <0>;

	qcom,dvm-val = <0xffffffff>;

};

Example for DDR4/DDR5 specific part:

qcom,gpu-pwrlevel@6 {

	reg = <6>;

	qcom,gpu-freq = <480000000>;

	/* DDR5 */

	qcom,bus-freq-ddr8 = <10>;

	qcom,bus-min-ddr8 = <9>;

	qcom,bus-max-ddr8 = <11>;

	/* DDR 4 */

	qcom,bus-freq-ddr7 = <9>;

	qcom,bus-min-ddr7 = <7>;

	qcom,bus-max-ddr7 = <9>;

	qcom,dvm-val = <0xffffffff>;

};

#include <linux/sched.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/of_fdt.h>

#include <linux/delay.h>

#include <linux/input.h>

#include <linux/io.h>

	int ret = of_property_read_u32(node, prop, ptr);

	if (ret)

		dev_err(dev, "Unable to read '%s'\n", prop);

		dev_err(dev, "%pOF: Unable to read '%s'\n", node, prop);

	return ret;

}

	}

}

static int _of_property_read_ddrtype(struct device_node *node, const char *base,

		u32 *ptr)

{

	char str[32];

	int ddr = of_fdt_get_ddrtype();

	/* of_fdt_get_ddrtype returns error if the DDR type isn't determined */

	if (ddr >= 0) {

		int ret;

		/* Construct expanded string for the DDR type  */

		ret = snprintf(str, sizeof(str), "%s-ddr%d", base, ddr);

		/* WARN_ON() if the array size was too small for the string */

		if (WARN_ON(ret > sizeof(str)))

			return -ENOMEM;

		/* Read the expanded string */

		if (!of_property_read_u32(node, str, ptr))

			return 0;

	}

	/* Read the default string */

	return of_property_read_u32(node, base, ptr);

}

static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev,

		struct device_node *node)

{

		if (index >= KGSL_MAX_PWRLEVELS) {

			dev_err(device->dev,

				"Pwrlevel index %d is out of range\n", index);

				"%pOF: Pwrlevel index %d is out of range\n",

					child, index);

			continue;

		}

			&level->gpu_freq))

			return -EINVAL;

		if (adreno_of_read_property(device->dev, child, "qcom,bus-freq",

			&level->bus_freq))

			return -EINVAL;

		ret = _of_property_read_ddrtype(child,

			"qcom,bus-freq", &level->bus_freq);

		if (ret) {

			dev_err(device->dev,

				"%pOF: Couldn't read the bus frequency for power level %d\n",

				child, index);

			return ret;

		}

		if (of_property_read_u32(child, "qcom,bus-min",

			&level->bus_min))

		level->bus_min = level->bus_freq;

		_of_property_read_ddrtype(child,

			"qcom,bus-min", &level->bus_min);

		if (of_property_read_u32(child, "qcom,bus-max",

			&level->bus_max))

		level->bus_max = level->bus_freq;

		_of_property_read_ddrtype(child,

			"qcom,bus-max", &level->bus_max);

	}

	return 0;

}

static void adreno_of_get_initial_pwrlevel(struct adreno_device *adreno_dev,

		struct device_node *node)

{